Abstract

A generic flow chart of the digital signal processing (DSP) optical reception systems is introduced in Figure 6.1. It is noted that the clock/timing recovered signals is fed back into the sampling unit of the analog-to-digital converter (ADC) so as to obtain the best correct timing for sampling the incoming data sequence for processing in the DSP. Any errors made at this stage of timing will result into high deviation of the bit-error rate (BER) in the symbol decoder shown in Figure 6.1. It is also noted that the vertical polarized channel (V-pol) and the horizontal polarized (H-pol) channel are detected and their in-phase (I-) and quadrature (Q-) components are produced in the electrical domain with signal voltage conditioned for the conversion to the digital domain by the ADC. Figure 6.1