Abstract

Recent development of lithography techniques has made it possible to fabricate patterns with a few tens of nanometers. Accordingly, a gate length of the advanced CMOS (complementary metal oxide semiconductor) transistors could be <10 nm. The semiconductor roadmap suggests that the limit of the size miniaturization of the transistors would come in the near future. The main problem of the present CMOS transistor is an increase of power consumption due to the leakage current in addition to the difficulty of the size miniaturization. Various attempts have been carried out to overcome the problems without changing the operation principle of the transistor. This strategy is the so-called More Moore. There are two other approaches to overcome the problem. One is the so-called More than Moore, in which conventional integrated circuits (ICs) are combined with sensors and other functionalities to enhance the function of the chip. The other is the so-called Beyond CMOS, in which completely new devices will be explored. “Nanoelectronics” means different things to different people. In this chapter, I will limit myself to “Beyond CMOS.” But, the “Beyond CMOS” may still include many things, and sometimes a concrete image of the devices is not established. For example, “Spintronics” is often used as concepts for one of the “Beyond CMOS” possibilities. In general, it uses “spin” instead of “charge.” However, spintronic devices that have a concrete device image may be TMR (tunneling magnetoresistance) and GMR (giant magnetoresistance) devices, MRAM (magnetic random access memory), and a spin transistor (Waser 2005). Some of these need to be in “nano” scale, but others are not necessarily in nanoscale. Besides the device aspect, the field is attracting increasing interests from the basic physics point of view. Spin currents, the spin Hall effect, and topological currents are among those (Takahashi and Maekawa 2008). Because of the limitation of pages, I will focus on some specific topics that are essential in nanoscale.