ABSTRACT
Silicon CMOS technology has been, by far, the dominant technology in the semiconductor industry for the last three decades. In particular, digital applications ranging from everyday microprocessors used in computers and cellular phones to state-of-the-art servers are almost exclusively dominated by silicon CMOS devices, owing to their (relatively) low cost and complexity, and their historically low power consumption. With scaling, in addition to the digital switching speed, analog and RF performance of CMOS devices has improved to the point where these devices are making significant inroads in the realm of analog and RF design that have historically been dominated by highspeed silicon bipolar and III–V technologies [1,2]. The dominance of silicon CMOS devices in digital applications and their increasing penetration in analog applications imply that any commercial-off-the-shelf technology used in extreme environments will include a large number of CMOS devices performing critical functions. It is therefore important to understand and predict the behavior of CMOS devices in extreme environments.
