ABSTRACT
CMOS-based radio frequency (RF) and analog systems have made rapid inroads into the analog/wireless market in recent years [1–3]. Today, most of the CMOS-based commercial analog/RF circuits and systems are based on 180 or 130 nm technologies (because of better device models and lower cost of these matured technologies). The digital-driven CMOS scaling into the sub-100 nm range has produced transistors with competitive RF performance characteristics (f T,fMAX , linearity, power gain, noise) (see Figure 17.1) [4]. With such scaling, however, the short-channel effects can degrade circuit performance. Silicon-on-insulator (SOI) technology has been widely adopted to help mitigate these short-channel effects [5,6]. Decreasing device dimensions at similar power supply has resulted in transistors with increasing intrinsic electric fields and hence increasing reliability concerns. In general, there is expected to be some degradation in device parameters under extreme operation conditions such as large voltage swings, large RF stress, etc. [7–9]. This can lead to degradation in circuit and system-level performance [10,11]. In sub-100 nm CMOS technologies, the device parasitics have a large impact on the performance and reliability of the device itself and of the circuits using them. Thus the knowledge of these trade-offs between performance and reliability is essential for the design of high-performance and reliable circuits, and will be the focus of this chapter. Ideally, such trade-offs should be included in the transistor compact models. However, building such models can be a challenge because of their high cost and complexity. Thus the onus is upon the sub-100 nm CMOS circuit designers to understand and apply these trade-offs to achieve the design specifications and at the same time meet the 10 year lifetime requirement [12]. Cutoff frequency (<italic>f</italic> <sub>T</sub>) as a function of drain current for the different RF-CMOS technologies. https://s3-euw1-ap-pe-df-pch-content-public-u.s3.eu-west-1.amazonaws.com/9781315216911/9fc10d54-04ca-4e8b-af21-9892cbc5b25d/content/fig17_1.tif"/> (From Jan, C.-H., Agostinelli, M., Deshpande, H., El-Tanani, M.A., Hafez, W., Jalan, U., Janbay, L., Kang, M., Lakdawala, H., Lin, J., Lu, Y.-L., Mudanai, S., Park, J., Rahman, A., Rizk, J., Shin, W.-K., Soumyanath, K., Tashiro, H., Tsai, C., VanDerVoorn, P., Yeh, J.-Y., and Bai, P., RF CMOS technology scaling in high-k/metal gate era for RF SoC (system-on-chip) applications, in Proceedings of the 2010 IEEE International Electron Devices Meeting, San Francisco, CA, 2010, pp. 27.2.1–21.2.4. © 2010 IEEE.)
