ABSTRACT
Complex mixed-signal systems, whether they are SiP or SoC designs, involve the merging of divergent analog and digital design flows. Digital IC design flows are classically text-based and leverage event-driven digital simulators. Realization of the digital circuitry is availed by synthesis and timing closure tools. Simulation cycles are often minutes to hours and set an expectation for the schedule/coverage trade-offs of the SiP chip-set. In contrast, analog IC design flows are classically schematic-based and are verified with analog solvers like SPICE [1]. The simulation times increase geometrically with higher levels of integration where impact on schedule can easily reach days or weeks, making SiP level simulation coverage intractable using the classical design flows.
