ABSTRACT

Researchers have been predicting limitations to the size scaling for CMOS (complementary metal–oxide–semiconductor)-integrated circuitry for many years. Often, these limits have been overcome and extended to smaller and smaller sizes [1]. However, as the CMOS minimum feature size has continued to shrink over the past decade, other concerns which are less fundamental and more practical have arisen. A particularly well-known example of this fact can be seen with limitations on the CPU clock speed due to power dissipation challenges. In response to this effect, CPU designers have resorted to techniques such as integrating multiple core CPUs in attempting to maintain the exponential computing performance growth which has driven the multibillion dollar industry for several decades. However, multi-core performance advantages also have limitations stemming from the ability to parallelize applications which will limit their effectiveness to increase practical performance [2]. In response to issues such as these, academia and industry have been researching alternative technologies to extend and replace CMOS designs in the coming years. However, these technologies have suffered from their own theoretical and practical challenges and thus a clear alternative for CMOS circuitry has not yet emerged.