Graphene-on-Diamond Devices and Interconnects

Graphene is a promising material for future electronics owing to its extremely high carrier mobility [1–3], thermal conductivity [4,5], saturation velocity [2,3], and ability to integrate with almost any substrate [6]. The most feasible are applications that do not require a bandgap but can capitalize on graphene’s superior current-carrying capacity. Graphene field-effect transistors (FETs) and interconnects built on SiO₂/Si substrates reveal the breakdown current density, J _BR , of ~1 μA/nm² [7–9], which is ~100 × larger than the fundamental electromigration limit for the metals [10]. However, the current-carrying capacity of graphene-on-SiO₂/Si devices is still smaller than the maximum achieved in carbon nanotubes (CNTs) [11–13]. In this chapter, we outline the graphene-on-diamond technology, which enables the fabrication of graphene-on-diamond devices and interconnects with a substantially enhanced breakdown current density. The discussion in this chapter follows our report of a systematic study of the current-induced breakdown in graphene-on-diamond devices [14]. The study demonstrated that by replacing SiO₂ with a synthetic diamond, one can solve the early-graphene-device-failure problem and increase J _BR of graphene by an order of magnitude to above ~10 μA/nm² [14]. We used recent advances in the chemical vapor deposition (CVD) and processing of diamond for fabricating >40 graphene devices on ultra-nanocrystalline diamond (UNCD) and single-crystal diamond (SCD) substrates with a surface roughness below δH ≈ 1 nm. It was found that not only SCD but also UNCD with a grain size D ~ 5–10 nm can improve J _BR , owing to the increased thermal conductivity of UNCD at higher temperatures. The obtained results are important for graphene applications in interconnects [7,15] and radio-frequency transistors [16], and can lead to the new planar sp²-on-sp³ carbon-on-carbon technology.