ABSTRACT

To date, feature sizes in complementary metal–oxide–semiconductor (CMOS) technologies have been scaled from 3 μm to sub-nanometers using the “top-down” scaling techniques [1]. In the sub-nanometers regime, miniaturization with the top-down techniques is not only becoming complex and expensive but also it is limited by the spatial resolution of lithography, variability, and longer fabrication turnaround times [2–4]. To overcome these issues, “bottom-up” nanotechnologies or the combination of bottom-up and top-down fabrication methodologies can be used to fabricate devices [5–8]. This approach provides a way to fabricate devices with feature sizes smaller than 10 nm, three-dimensional complex nanostructures and to make devices with novel functionalities (Figure 4.1). Top-down fabrication involving patterning, lithography, and etching versus bottom-up self-assembly process. https://s3-euw1-ap-pe-df-pch-content-public-u.s3.eu-west-1.amazonaws.com/9781315216089/1a39fa69-e426-4ca1-a1b7-b7d35c28e418/content/fig4_1.tif"/>