ABSTRACT
Computer architecture constitutes one of the key and strategic application fields for new, emerging devices at nanoscale dimensions, potentially getting benefit from the expected high-component density and speed. However, these future technologies are expected to suffer from a reduced device quality, exhibiting a high level of process and environmental variations as well as performance degradation due to the high stress of materials [1–4]. This clearly indicates that if we are to make use of those novel devices, we have to rely on fault-tolerant architectures. Currently, most of the redundancy-based fault-tolerant architectures make use of majority gates (MAJ) [5,6] and require high area overhead. An alternative to majority gate voting is the averaging cell (AVG) [7–9], which can exhibit higher reliability at a lower cost. The underlying principle of the AVG is to average several input replicas in order to compute the most probable output value. This approach is quite effective in case the AVG inputs are subject to independent drifts with the same/similar magnitude. In practice, however, input deviations can be nonhomogeneous, in which case the balanced average cannot provide a response that minimizes the output error probability.
