Contents
Contents
Silicon device technology scaling and performance improvement require [1–3] not only overcoming a variety of fabrication challenges but also suppressing systematic variation and random effects [4–7]. Except process variation effect (PVE), random dopant fluctuation (RDF), as one of the known major intrinsic parameter fluctuations, complicates device manufacturing and degrades device characteristics in the nanometer scale complementary metal–oxide semiconductor (nanoCMOS) device era [8–30]. Highκ/metalgate (HKMG) technology has been a key way to suppress RDFinduced variability and reduce leakage current [31–38]; however, HKMG may introduce random interface traps (ITs) at a highκ/silicon interface and such IT fluctuation (ITF) degrades device characteristics considerably [39–47]. Various simulations of the device’s variability induced by ITF were reported by using a onedimensional (1D) IT’s model for sub65nm CMOS devices [46], a 2D IT’s model for 16nmgate HKMG devices [39], local interaction of the combined RDs and ITs [40,41], and full fluctuation among all random sources [4]. Recently, the asymmetric RDF on device characteristics was studied for 16nmgate HKMG metal–oxide–semiconductor field effect transistor (MOSFET) devices [48,49]. However, induced by random ITs, asymmetric physical and electrical characteristic fluctuations of 16nmgate HKMG MOSFETs have not been discussed yet.
In this chapter, the asymmetric characteristic fluctuation of the random ITs in 16nmgate HKMG MOSFETs is presented. Random ITs at the 2D interface of the hafnium oxide (HfO_{2})/silicon of the 16nmgate HKMG NMOSFETs are incorporated into an experimentally validated 3D device simulation [11] to quantify the random ITsfluctuated characteristics. Largescale statistical 3D device simulation is performed by solving a set of calibrated 3D electron–hole densitygradient equations coupling with the Poisson equation as well as electron–hole current continuity equations [50,51]. On the basis of the largescale statistical 3D device simulation of random ITsfluctuated samples, the random ITsinduced threshold voltage fluctuation (σ_{Vth}) and on/offstate current fluctuation are estimated and compared with other significant fluctuation sources. In particular, an asymmetric draininduced, barrierlowering fluctuation σ_{DIBL} and a subthreshold swing fluctuation σ_{SS} [1] are studied by classifying the random ITs into the regions near the source side, around the middle of the channel, and near the drain side of the silicon channel, respectively. Our quantum mechanically corrected device simulation was compared with experimental data aiming at the greatest accuracy [11], which further enables us to explore both the individual and combined effects of randomly existing ITs and RDs on device characteristics in a unified way. The random 2D ITs are also solved with 3D RDs inside the silicon channel at the same time to assess the interaction effect of the combined ITs and RDs. For the studied 16nmgate HKMG NMOSFETs with a device width of 16 nm, the high density of ITs (D_{it}) in the range of 3 × 10^{11}−3.3 × 10^{12} eV^{−1}cm^{−2} results in 26.3 mV fluctuation of threshold voltage and for the low D_{it} varying from 2.5 × 10^{10} to 3.8 × 10^{11} eV^{−1}cm^{−2}. Both the high and low D_{it}induced σ_{Vth,ITs} are smaller than that of σ_{Vth,RDs} = 43 mV. The largest asymmetric values of σ_{Vth} and σ_{SS} are observed when random ITs with high D_{it} are near the source side, compared with the random ITs located at the middle of the channel and near the drain side. The engineering findings of this study indicate that both the ITs near the source side of the silicon channel and the RDs near the channel surface possess the largest characteristic fluctuations.
This chapter is organized as follows. In Section 3.2, we describe the simulation settings for random ITs, RDs, and the combined ITs and RDs (denoted as “ITs + RDs”)induced device and circuit’s characteristic fluctuations. In Section 3.3, we discuss the findings of this study for the random ITsfluctuated 16nmgate devices as well as the static randomaccess memory (SRAM). Finally, we draw conclusions and suggest future work.
The devices we examined are the 16nmgate titaniumnitride (TiN) gate MOSFETs with an amorphousbased TiN/HfO_{2} gate stack which has an effective oxide thickness (EOT) of 0.8 nm, as shown in Figure 3.1a. The EOT varying from 0.4 to 1.2 nm will also be simulated for examining the impact of different highκ gate stacks on fluctuation suppression. Note that the device’s width is equal to the gate length of 16 nm, which is designed for the most critical assessment. The validated nominal device characteristics of the studied 16nmgate HKMG MOSFETs are calibrated, where the magnitude of the threshold voltages of the 16nmgate N and PMOSFETs is 250 mV. To examine the asymmetric characteristic fluctuation induced by random ITs, as shown in Figure 3.1a, we have partitioned the channel into three different regions: random ITs near the source side, around the middle of the channel, and near the drain side.
To carry out the statistical 3D device simulation with random ITs at HfO_{2}/Si interface, we first randomly generate 753 acceptorlike ITs (gray dots), as shown in Figure 3.1b, in a large 2D plane of (224 nm)^{2} where the random ITs’ concentration is around 1.5 × 10^{12} cm^{−2} in the large plane. Notably, this value is mainly for statistically generating the number of random ITs, which is not equal to the effective entire density of ITs (D_{it}). The total number of generated random ITs follows the Poisson distribution [1,42–47]. The large plane is then partitioned into many subplanes, where the size of each subplane is 16 nm^{2}. The number of random ITs in each subplane varies from 1 to 8 and the average number of ITs is 4, as shown in the histogram bar chart of Figure 3.1b. Each IT’s energy on a subplane is randomly assigned according to the relation of D_{it} versus the energy [1,42–47], as shown in Figure 3.1b; consequently, each IT’s density can be estimated according to its randomly assigned energy and the D_{it} may vary randomly from 1 × 10^{10} to 1 × 10^{12} eV^{−1} cm^{−2}, which quantitatively coincides with our experimental characterization for sub20nm HKMG CMOS devices. We repeat this process until all subregions are assigned. Therefore, 196 randomly generated 3D device samples with 2D random ITs at the HfO_{2}/Si interface are simulated to assess the influence of ITF.
For the RDF simulation, we mainly follow the simulation procedure reported in our recent work [4,8–13]. As shown in Figure 3.1c, the RDs in the 3D device channel region are statistically incorporated into the statistical 3D device simulation running on our parallel computing system [52]. Note that, for the best accuracy of our computational model, the implemented statistical 3D device simulation technique for estimating characteristic fluctuation was experimentally validated with silicon data for sub20nm devices in our earlier work [11], where the RDsfluctuated mobility was validated with experimentally measured current–voltage (I–V) data. To compare with other significant fluctuation sources, such as PVE, oxide thickness fluctuation (OTF), and work function fluctuation (WKF) with different sized TiN grain, we follow the simulation procedures reported in our recent work [4].
Figure 3.1 (a) Illustration of the studied device together with two sources of randomness: interface traps (gray dots) located at the HfO2/Si interface and random dopants (dark dots) located at the silicon channel. Interface traps (ITs) inside three different regions of the channel are classified according to the ITs’ location. They are, ITs near the source side, ITs around the middle of the channel and ITs near the drain side. Statistical 3D device simulation settings for the characteristic fluctuation resulting from random ITs and random dopants (RDs) are shown in (b) and (c). (b) We first generate 753 acceptorlike traps in a large plane for the 16nmgate NMOSFET devices, where the IT’s concentration at the large plane of (224 nm)2 is around 1.5 × 1012 cm−2 and the total number of generated ITs follows the Poisson distribution. Each IT’s energy on the plane is independently assigned according to the distribution of its density. Then, the entire plane is partitioned into many subplanes of (16 nm)2 corresponding to the device’s size, where the number of ITs in each subplane may vary from 1 to 8 and the average number is 4. Thus, the effective density of interface traps (Dit) varies from 3 × 1011 to 3.3 × 1012 eV−1cm−2. We call the ITs with high Dit for device Dit ranging from 3 × 1011 to 3.3 × 1012 eV−1 cm−2 and the ITs with low Dit for device Dit ranging from 2.5 × 1010 to 3.8 × 1011 eV−1cm−2. (c) For the setting of discrete dopants, impurities are randomly generated and distributed in a (96 nm)3 cube with an average concentration of 1.5 × 1018 cm−3. There will be 1327 discrete dopants within the cube, and the number of discrete dopants varies from 0 to 14 (the average number is six) for all 216 subcubes of (16 nm)3, which corresponds to the volume of the studied devices. Consequently, the total subcubes and subplanes can be mapped into the device’s 3D channel and 2D surface for the characteristic fluctuation induced by the ITs, RDs, and combined ITs and RDs, respectively.
The statistically generated ITs are further implemented for 16nmgate PMOSFET devices so that the 16nmgate CMOS SRAM circuit can be simulated using coupled device–circuit solution methodology [13] to estimate the transfer characteristic fluctuation at the circuit level, as shown in Figure 3.2a. The computational flow of the coupled device–circuit simulation is shown in Figure 3.2b. Owing to the lack of wellestablished compact models for the 16nmgate CMOS devices, by using the coupled device–circuit simulation technique, the circuitlevel fluctuations are estimated for the CMOS SRAM circuit, as shown in Figure 3.2a. To estimate the SRAM’s static noise margin fluctuation σ_{SNM}, electrical characteristics of each randomly generated device in the tested circuit are first calculated by the 3D device simulation. The obtained result is then used as the devices’ terminal characteristics in the coupled device–circuit steadystate simulation. The nodal equations of the tested SRAM circuit are formulated and then directly coupled to the device transport equations (in the form of a large matrix that contains both circuit and device equations), which are solved simultaneously to obtain the circuit transfer characteristics. The device characteristics obtained by device simulation, such as the distributions of potential and current density, are input in the SRAM circuit simulation through the device’s contact terminals. Notably, to explore the influence of the intrinsic parameter fluctuation of σ_{SNM} of the SRAM circuit, the random samples are generated and performed, respectively.
Figure 3.2 (a) To calculate the σSNM, the totally random generated N and PMOSFET devices with different random sources are assigned into the 6T SRAM circuit for the coupled devicecircuit simulation. (b) The proposed flowchart for the coupled devicecircuit simulation. Notably, the voltage of node N2(V) in the simulated 6T SRAM circuit is applied to 0.8 V. To assess the worst influences of ITs, RDs, and combined ITs and RDs on the 16nmgate SRAM’s transfer characteristics, the cell ratio is set to 1 for all simulations.
First, we explore the random ITsfluctuated terminal current; Figure 3.3a shows the totally random ITsinduced fluctuations of drain current–gate voltage (I_{D}−V_{G}) curves of the 16nmgate NMOSFETs with high D_{it}, where the line with circles indicates the nominal case and all dashed lines are the random ITsfluctuated cases. The nominal case is the fresh device without random ITs. The random ITs located at the HfO_{2}/silicon interface may destroy the screening effect and the threshold voltage is simply raised. As shown in Figure 3.3b, the value of threshold voltage is determined from a constant current criterion when the drain current is greater than 10^{−7} × (W/L) A, where L and W are the gate length and device width, respectively. The threshold voltage increases, and then the on/offstate current (I_{on}/I_{off}) decreases accordingly, as the number of random ITs increases. The simulated σ_{Vth,ITS} is 26.3 mV, which is smaller than the result of RDF (σ_{Vth,RDs} = 43 mV). The random ITsposition induced different fluctuations of characteristics in spite of having the same number of ITs, as marked by an open bar in the inset of Figure 3.3b, where the magnitude of the spread characteristics of the threshold voltage increases as the number of random ITs increases. Figures 3.3b and c show the extracted I_{on} and I_{off} as functions of the number of random ITs, where each symbol shows each random ITfluctuated result. The magnitude of each random ITsfluctuated current decreases as the number of random ITs increases. Similarly, the random ITsposition induced rather different current fluctuations in spite of having the same number of random ITs, as marked by an open bar in insets of Figures 3.3c and d. To explore the impact of the random position of ITs on the device’s physical characteristics, as shown in Figure 3.4, the random ITsfluctuated surface potential and the electron current density from the source side to the drain side for the device at the onstate condition are further discussed. Three cases are selected among 196 simulations to demonstrate the random position associated local repulsive Coulomb field and disturbed electron current conducting path at the HfO_{2}/Si interface. Figure 3.4a shows the plots for the case of the random 4 ITs near the source side. Compared with the random ITs appearing in the other two regions, as shown in Figures 3.4b and c, the distribution of electron current density is seriously destroyed because of the random 4 ITs near the source side locally, which results in a relatively higher local spike of potential barriers and thus raises the threshold voltage (V_{th} = 316 mV). Figures 3.4b and c show plots for the case of the random 4 ITs around the middle of the channel and for the case of the random 4 ITs near the drain side. These random 4 ITs positioning away from the source side have relatively weakened local spikes of potential barriers which still effectively impede electron current conduction; however, they are weaker than that of the random 4 ITs appearing in the source side, as shown in Figure 3.4a. Thus, the device with random ITs of Figure 3.4c has minimal threshold voltage (V_{th} = 257 mV) and the largest area of electron current conduction, compared with the case of Figure 3.4a. The asymmetric impact of random ITs on the surface potential results in quite different threshold voltage as well as the variance of the threshold voltage, as listed in Table 3.1. The statistically simulated I_{D} − V_{G} curves enable us to extract the σ_{Vth}, induced by different sources of fluctuations among different regions. As listed in Table 3.1, the ITF inducedσ_{Vth} and σ_{SS} for the device with random ITs near the source side, around the middle of the channel, and near the drain side, respectively, are further calculated and classified. The studied 16nmgate NMOSFETs with both the high and low D_{it} of ITs are simulated; significant values of σ_{Vth} and σ_{SS} induced by random ITs with high D_{it} near the source side are observed, compared with the random ITs located at the middle of the channel and near the drain side. However, the simulation indicates that there is no differences in σ_{Vth} and σ_{SS} for the cases of random ITs located at the middle of the channel and near the drain side. In particular, for a device with a low D_{it}, near the source side, the σ_{Vth} is reduced from 28.7 to 10.2 mV; similarly, the σ_{SS} is reduced from 21.2 to 5.6 mV/Dec. The impact of RDs on the threshold voltage, SS, and DIBL, among the aforementioned three regions is insignificant, but the impact of RDs near the channel surface is different from RDs located away from the depletion region of the channel [8–13,48,49].
Figure 3.3 (a) The plot of ITsfluctuated ID−VG curves shows the random ITsinduced DC characteristic fluctuations for the studied devices. The line with circles is the nominal case calibrated to Vth = 250 mV and others are the random ITsfluctuated cases. From the ID−VG curve, we can extract the threshold voltage fluctuation, the offstate current fluctuation, and the onstate current fluctuation with respect to the number of ITs, as shown in (b), (c), and (d), respectively. We observe that the threshold voltage is increased, and thus the offstate current and the onstate current are decreased as the number of ITs is increased due to the relatively higher barriers generated. Except for the random number effect of ITs, the random position effect of ITs results in different threshold voltage for the same number of ITs.
Figure 3.4 Plots of the ITsfluctuated surface potential and the electron current density from the source side to the drain side for the device at the onstate condition. (a) Plots for the case of ITs near the source side. (b) Plots for the case of ITs around the middle of the channel. (c) Plots for the case of ITs near the drain side. The asymmetric impact of ITs on the surface potential results in different threshold voltage as well as a variance in the threshold voltage, as listed in Table 3.1.
σ_{Vth} (mV) 
σ_{ss} (mV/Dec) 


Near Source Side 
Around the Middle of the Channel 
Near Drain Side 
Near Source Side 
Around the Middle of the Channel 
Near Drain Side 

High D_{it} 
28.7 
25.0 
23.1 
21.2 
4.6 
5.1 
Low D_{it} 
10.2 
7.7 
7.5 
5.6 
4.0 
4.6 
Note: The studied 16nmgate NMOSFETs are with high and low D_{it} of ITs. Significant values of σ_{Vth} and σ_{SS} induced by random ITs near the source side are observed, compared with the ITs located at the middle of the channel and near the drain side.
The random ITsfluctuated DIBL effect is pronounced for the 16nmgate NMOSFETs, as shown in Figure 3.5a. For the device at the weak inversion region, there is a potential barrier at the channel region owing to a balance between the drift current and diffusion current. The barrier height decreases as the drain voltage increases; it thus results in an increased drain current, which is controlled not only by the gate voltage but also by the drain voltage. The DIBL effect could be observed through the I_{D} − V_{G} curves of a device under the linear (V_{D} = 0.05 V) and saturated (V_{D} = 0.8 V) regions. It can be calculated by the lateral shift of threshold voltage divided by the difference of the drain voltage and is given in units (mV/V). Figure 3.5a shows the random ITsfluctuated DIBL characteristic of the 16nmgate NMOSFETs; the magnitude of DIBL decreases as the number of random ITs increases because the random ITs reduce the probability of electricfield lines penetrating from the drain side to the source side. The tendency of increasing fluctuation of DIBL follows the threshold voltage as the number of random ITs increases, as shown in Figure 3.3b. Figure 3.5b shows that the device with a high D_{it} of random ITs near the source side has a large DIBL at the same number of random ITs; Figure 3.5c shows the device with a high D_{it} of random ITs around the middle of the channel which has a small DIBL at the same number of random ITs. The random position effect of ITs on the V_{th}, DIBL, SS strongly depends on the random ITs near the source side. Such asymmetric fluctuation was also observed for devices with RDF [48,49].
Figure 3.5 (a) The draininduced barrier lowering (DIBL) versus the number of ITs. (b) Device with a high Dit of ITs near the source side has high DIBL at the same number of ITs. (c) Device with a high Dit of ITs around the middle of the channel has low DIBL at the same number of ITs.
We now turn to compare the ITs, RDs, and “ITs + RDs”induced σ_{Vth} of the studied 16nmgate NMOSFETs. Figure 3.6 is the σ_{Vth} as a function of EOT with respect to different fluctuation sources: ITs (with high D_{it}), RDs, and “ITs + RDs.” The device with EOT = 0.8 nm exhibits σ_{Vth,RDs} = 43 mV, σ_{Vth,ITs} = 26.3 mV, and σ_{Vth,ITs+RDs} = 45.4 mV. We note that σ_{Vth,ITs+RDs} = 45.4 mV is smaller than the result calculated by $\sqrt{{{\sigma}^{2}}_{{\text{V}}_{\text{th},\text{ITs}}}+{{\sigma}^{2}}_{{\text{V}}_{\text{th,RDs}}}}=50.4\text{}\text{mV}$
in which the random variables following statistically independent identical distribution (iid) is assumed. However, the iid assumption on the random variables of V_{th,ITs} and V_{th,RDs} is not always true owing to the local interaction of surface potentials at different extents between ITs and RDs concurrently existing in the surface/channel region of the NMOSFETs. The relative error between σ_{Vth,ITs+RDs} and $\sqrt{{{\sigma}^{2}}_{{\text{V}}_{\text{th},\text{ITs}}}+{{\sigma}^{2}}_{{\text{V}}_{\text{th,RDs}}}}$ is about 11% overestimation, compared with the σ_{Vth,ITs+RDs} of the NMOSFETs; similarly, not shown here, the studied 16nmgate PMOSFETs has σ_{Vth,ITs+RDs} = 45.1 mV, which is smaller than the statistical sum $\sqrt{{{\sigma}^{2}}_{{\text{V}}_{\text{th},\text{ITs}}}+{{\sigma}^{2}}_{{\text{V}}_{\text{th,RDs}}}}=49.1\text{}\text{mV}$ . Owing to the sizable threshold voltage fluctuation with respect to EOT nonlinearly, the statistical sums of the variances of two random variables induced by ITs and RDs disclose significant errors, compared with the statistical 3D device simulation together with the combined ITs and RDs simultaneously. This investigation shows that the local interaction of surface potentials owing to “ITs + RDs” could not be calculated independently by using the results of ITs and RDs. It explains why the iid assumption overestimates the threshold voltage fluctuations induced by the combined ITs and RDs. As shown in Figure 3.7, the threshold voltage fluctuation induced by various random sources for the 16nmgate NMOSFETs, respectively, are compared. Among the five fluctuation sources, the RDF still dominates the σ_{Vth} and the PVE plays a sizable fluctuation source; both should be minimized by process innovation continuously. The WKFinduced σ_{Vth} is reduced from 36.7 to 11.1 mV when the minimal grain size of the TiN gate is reduced from (4 nm)^{2} to (2 nm)^{2}. The ITFinduced σ_{Vth} is reduced from 26.3 to 10.2 mV when the D_{it} is reduced from an order of 10^{12} to 10^{11} eV^{−1}cm^{−2}. We estimate the σ_{SNM} of the 6T SRAM circuit [53], as shown in Figure 3.2a. Butterfly curves fluctuation induced by RDF, PVE, WKF, and ITF of the tested 6T SRAM in read operation is first simulated, where the cell ratio CR = ((W/L)_{driver transistors:M1 and M2}/(W/L)_{access transistors:M5 and M6}) of the SRAM cell in this study is set as unitary, and the nominal value of SNM is 86 mV. They are then used to calculate σ_{SNM} with respect to different fluctuation sources, as listed in Table 3.2. The relation between the device transconductance and SNM of SRAM can be viewed as $\mathit{\text{SNM}}\propto \sqrt{1({I}_{\mathit{\text{nx}}}/{g}_{m,\mathit{\text{pmos}}})}({I}_{\mathit{\text{ax}}}/{g}_{m,n\mathit{\text{mos}}})$ , where I_{nx} is the saturation drain current of the driver transistor of SRAM and I_{ax} is the saturation drain current of the access transistor. The σ_{SNM} is directly proportional to the fluctuation of transconductance and the fluctuation of transconductance is influenced by the . Thus, σ_{SNM} induced by random ITs with high D_{it} has a minimal value of 19.1 mV because the is the lowest one among RDF, PVE, and WKF. However, the magnitude of σ_{SNM} for all RDF, PVE, WKF, and ITF is up to 20% of the nominal SNM, which may degrade the operation of 6T SRAM and should be improved by using multiple gate FETs or 8T SRAM cells [53].Figure 3.6 σVth as a function of EOT with respect to different fluctuation sources: ITs (with high Dit), RDs, and combined ITs and RDs (denoted as “ITs + RDs”). On the basis of the assumption of statistically independent identical distribution to the random variables of ITs and RDs, the σ2Vth,ITs+σ2Vth,RDsp is also calculated. Owing to the gate capacitance variation and surface potential interaction at different extents, resulting from combined ITs and RDs, the full 3D simulated is smaller than the result of σ2Vth,ITs+σ2Vth,RDsp.
Figure 3.7 The threshold voltage fluctuation induced by various random sources for the 16nmgate NMOSFETs. The WKFinduced σVth is reduced from 36.7 mV to 11.1 mV when the grain size of the metal gate is reduced from (4 nm)2 to (2 nm)2. The ITFinduced σVth is reduced from 26.3 mV to 10.2 mV when the effective density of the interface traps is reduced from high Dit to low Dit. Among fluctuations, the RDF dominates the σVth continuously and the PVE should be minimized.
Fluctuation Sources 
RDF 
PVE 
WKF (Grain Size: 4 nm^{2}) 
ITF (with High D_{it}) 

σ_{SNM} (mV) 
27.4 
20.8 
25.3 
19.1 
Note: σ_{SNM} induced by WKF is with 4nm metal grains and the σ_{SNM} induced by ITF is with high D_{it}.
In this chapter, the asymmetric characteristic fluctuation of the random ITs in 16nmgate HKMG MOSFETs has been presented. The random ITsinduced threshold voltage fluctuation and on/offstate current fluctuation, draininduced barrierlowering fluctuation, and subthreshold swing fluctuation have been studied by classifying the random ITs into the regions near the source side, around the middle of the channel, and near the drain side of the silicon channel, respectively. For the studied 16nmgate HKMG NMOSFETs with the device width of 16 nm, both high and low D_{it}induced σ_{Vth,ITs} are smaller than that of σ_{Vth,RDs} = 43 mV. The largest asymmetric values of σ_{Vth} and σ_{SS} have been observed when random ITs with high D_{it} are near the source side, compared with the random ITs located at the middle of the channel and near the drain side. The engineering findings of this study indicate that both the ITs near the source side of the silicon channel and RDs near the channel surface possess the largest characteristic fluctuations. The random ITs have also exhibited sizable σ_{SNM} of the 16nmgate 6T SRAM circuit, compared with the σ_{SNM} induced by RDF, PVE, and WKF.
This work was supported in part by the National Science Council (NSC), Taiwan, under contract no. NSC 1012221E009092 and by TSMC, Hsinchu, Taiwan, under a 2011–2013 grant.