ABSTRACT
Although polysilicon thin-film transistors (poly-Si TFTs) are attracting much attention for their use in active-matrix liquid crystal displays [1,2], fine-grain structures in the channel can affect their carrier transport and device performance. Poly-Si consists of a number of single-crystal grains. Between poly-Si grains, there exists a high defect density region called the grain boundary with a typical value of defect density ca. 1012 cm−2. Such a large number of randomly oriented grain boundaries usually cause large variations in the device’s electrical characteristics, including the threshold voltage and subthreshold swing (SS) [3]. Hence, several methods, including excimer laser annealing [4] and metal-induced lateral crystallization [5], have been developed to increase the grain size and minimize the grain boundary defects and thereby improve the electrical characteristics of poly-Si TFTs. Recently, a multiple-gate structure was reported in which the additional electric field enhanced the control over the channel surface potentials and the device performance, providing improved immunity to short channel effects [6,7]. In addition, TFT characteristics are dramatically improved upon reducing the channel width, particularly when using a nanowire (NW) as a channel [8,9]. Poly-Si TFTs featuring multiple NW channels exhibit improved performance relative to that of traditional planar devices because of the increment of effective channel width and the reduced grain boundary trap density in the channel region [10,11]. When the channel width and the poly-Si grain size are of the same order of magnitude, the random distribution of the grain boundary causes an even greater electrical fluctuation including threshold voltage and SS [9,12,13]. Therefore, uniformity of the grain boundary is critical when scaling down device dimensions.
