Mechanically Flexible Interconnects and TSVs

Applications in CMOS/MEMS Integration

Authored by: Hyung Suk Yang , Paragkumar Thadesar , Chaoqi Zhang , Muhannad Bakir

Noval Advances in Microsystems Technologies and their Applications

Print publication date:  July  2013
Online publication date:  April  2016

Print ISBN: 9781466560666
eBook ISBN: 9781466560673
Adobe ISBN:

10.1201/b15283-5

 

Abstract

The steady growth of the microelectromechanical systems (MEMS) industry over the last two decades has been nothing short of incredible. Currently, it is an $8B industry (as of 2010), and by the year 2015 it is projected to more than double and become a $17B industry (Eloy, 2010). Furthermore, what was a technology with a very limited number of commercial applications available for decades, namely, inkjet heads, digital light projectors (DLP) and automobile sensors systems, is now becoming ubiquitous (Marek and Gómez, 2012).

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Mechanically Flexible Interconnects and TSVs

3.1  Introduction

The steady growth of the microelectromechanical systems (MEMS) industry over the last two decades has been nothing short of incredible. Currently, it is an $8B industry (as of 2010), and by the year 2015 it is projected to more than double and become a $17B industry (Eloy, 2010). Furthermore, what was a technology with a very limited number of commercial applications available for decades, namely, inkjet heads, digital light projectors (DLP) and automobile sensors systems, is now becoming ubiquitous (Marek and Gómez, 2012).

However, despite the rapid growth of the industry, it is also hard to ignore the fact that the market is dominated by a very limited number of device types and also by very few MEMS powerhouses such as STMicroelectronics and Texas Instruments. Considering the vast interest and huge potential of MEMS technology demonstrated by the universities and research labs around the world, it is disappointing to see that the commercial world has not yet encompassed the full potential of MEMS device technology; emerging MEMS technology represents only 10% of MEMS market, and even those 10% is related to the reused existing devices in new applications or packaging or integration of the existing devices in a new way (MEMS Market Overview, 2010).

What is preventing new MEMS device technologies from being commercialized? One possible answer is the cost. MEMS devices, especially ones that require the use of novel materials or unconventional processes, are extremely costly to turn into a commercial product due to what Yole Development call MEMS law – ‘One product, one process, one package.’ (MEMS Market Overview, 2010) This MEMS law refers to the observed trend that fabrication processes and packages needed by MEMS devices are so unique to those devices that both the fabrication processes and packages cannot be standardized, and therefore, both need to be custom designed for each unique product. Compared to the microelectronics industry where many small successful fabless companies exist, taking advantage of dedicated foundry like TSMC to handle fabrication and packaging needs, many of the MEMS companies require a significant initial investment.

This makes it difficult for a completely new MEMS technology or new companies to enter the market. Naturally more effort is being spent in finding new applications for existing devices and packaging existing devices in more efficient and cost-­effective manner as noted previously.

However, there are emerging integration and packaging technologies for MEMS that aim to address this issue in the market. These technologies aim to create a generic integration scheme and packaging platform that can be used by a wide range of MEMS (and sensors) devices without a significant modification or engineering.

Specifically, by leveraging new advances in flexible I/O technologies and through-silicon vertical interconnect access (via) (TSV) technologies, one can create a generic integration platform for state-of-the-art complementary metal oxide semiconductor (CMOS) and arbitrary MEMS devices.

3.2  Need for Integration of Mems and Circuitry

In order for a system incorporating MEMS devices to operate, the devices must be connected to a read-out (sensors) or a driving circuitry (actuators). This is because signals from the MEMS transducer devices produce very small signals and require signal conditioning, amplification and in many cases conversion to digital signals (Baltes et al., 2005).

For example, a modern capacitive accelerometer device designed by Jiangfeng et al. (2004) has a device output sensitivity of 0.6 fF/g and a linear range of +/−6 g. This means that the circuit must be capable of resolving capacitance changes in the ∼10 aF range. Of course, the ability to resolve such a small signal is often a function of both circuit design and device design; fundamentally however, performance of the interconnect technology connecting the device and the circuit also plays a significant role.

Specifically, in capacitive sensing systems, parasitic capacitance of the circuit is correlated to the minimum detectable capacitance (resolution) (Yazdi et al., 2004; Seraji and Yavari, 2011). Despite the differences in the degree of sensitivity to the parasitic capacitance in various types of circuits used, it is possible to discern that an increase in the parasitic capacitance will increase the minimum detectable capacitance change in all cases, thereby resulting in the reduction of the sensitivity and overall resolution of the system (Yazdi et al., 2004). For some circuits where the effective parasitic capacitance is not reduced using techniques such as bootstrapping, it can also attenuate the signal at the input of the amplifier circuit, in turn affecting the sensitivity and resolution of the system even more. For high-frequency systems, other parasitic parameters play an important role; Joseph et al. (2008) shows that inductance of interconnects plays an important role in determining the performance of the RF system.

What is evident is that, for a system that involves MEMS or sensors, the interconnect performance plays a vital role in determining the overall performance of the system; for an integration and packaging platform capable of providing low parasitic interconnects is just as important as the performance of individual devices.

3.3  Conventional Method of Integration

For reasons stated in the previous section, the integration technologies for MEMS is a vital part of the system development that determines what type of interconnects are available for use. In modern systems, one can broadly categorize packaging and integration methods of MEMS into two categories: monolithic integration and hybrid integration. Most MEMS products currently in the market use one of these two methods, each with both disadvantages and advantages.

3.3.1  Monolithic Integration

Monolithic integration is when the CMOS and MEMS are fabricated in the same silicon chip as shown in Figure 3.1. Due to the use of on-chip interconnects for connecting MEMS devices to required circuits, this method of integration has a very low parasitic capacitance; though the capacitance depends on the length of interconnects, Fedder (1998) reports on-chip interconnect capacitance of 0.017 pF and approximately 0.3 pF/mm (Krishnamoorthy et al., 2011). Also, due to the fine pitch wires available with the CMOS IC’s back-end-of-the-line (BEOL) process, even a large array of MEMS/sensors can be individually interconnected. Monolithically integrated chips, which contain both CMOS and MEMS, are fabricated at the wafer level; therefore, the unit cost can also be lowered significantly.

There are three general approaches in monolithic integration of CMOS and MEMS:

  1. Pre-CMOS – MEMS before CMOS
  2. Intra-CMOS – MEMS between FEOL and BEOL
  3. Post-CMOS – MEMS after CMOS

Monolithic integration of CMOS and MEMS.

Figure 3.1   Monolithic integration of CMOS and MEMS.

The main differences between the three are related to when the MEMS devices are fabricated with respect to CMOS’ front-end-of-the-line (FEOL) and BEOL processes. The choice of the approach used will largely depend on the material and processes required for the fabrication of MEMS devices. This is due to the fact that presence of two dissimilar technologies in the same substrate imposes many restrictions on processes and materials one can use for CMOS and MEMS processes. The restriction is often based on technical reasons including

  • Different doping requirement of the Si substrate by CMOS and MEMS; both CMOS device and bulk Si etch common in MEMS are sensitive to doping type and concentration and require unconventional starting Si wafer to be used (Muller et al., 2000).
  • Thermal budget available during the post-processing; long thermal process and/or high-temperature process can change the doping profile and alter device characteristics (Sedky et al., 2001). Studies like Huang et al. (2008) show an example additional effort required in trying to keep thermal processes in MEMS under certain temperature.
  • Permitted material available due to process compatibility concerns; materials that introduce impurity and/or are incompatible with CMOS process, such as metals, can only be used selectively. Materials such as poly-Si are commonly used as conductors.

Sometimes the restriction is based on practical and economic reason as well; for example, a state-of-the-art CMOS foundry will be unlikely to process your wafers with MEMS already present on it due to contamination concerns. This means that without an in-house fabrication capability, post-CMOS MEMS process is the only likely option available for most MEMS designers. As a result, monolithic integration’s nonrecurring cost, which includes research and development cost, is quiet high.

In summary, the monolithic integration provides low parasitic interconnections, a high-performance circuitry, low unit cost and ability to integrate a large array of MEMS/sensor devices; however, it is a complex and expensive process to develop that may impose significant restriction on the fabrication of MEMS devices. As a result, monolithic integration is used by MEMS products that require high-performance integration and by products that expect a large sale volume.

3.3.2  Hybrid Integration

On the opposite end of spectrum to monolithic integration is the hybrid integration, also known as the package-based integration. Hybrid integration refers to configurations where MEMS and CMOS are fabricated on separate chips using completely independent processes and then assembled onto the same package substrate.

This is currently the most commonly used method of integrating CMOS and MEMS (Witvrouw, 2006). This is because, unlike monolithic integration, the integration method allows arbitrary MEMS chips and state-of-the-art CMOS ICs to be integrated with relative ease; CMOS ICs and MEMS chips are fabricated independently, and as a result, both CMOS and MEMS fabrications can be done without being limited to specific materials or processes as it is the case with the monolithic integration.

Unfortunately, unlike monolithic integration where MEMS and CMOS interconnections are provided by short, low parasitic on-chip interconnects, hybrid integration requires the use of either

  1. Long on-chip interconnect to redistribute signal to chip’s perimeter and wire bond (Figure 3.2) or
  2. Flip-chip bonding with long wires on the package substrate (Figure 3.3)

Hybrid integration of CMOS and MEMS using wirebonds.

Figure 3.2   Hybrid integration of CMOS and MEMS using wirebonds.

Hybrid integration of CMOS and MEMS using flip chip.

Figure 3.3   Hybrid integration of CMOS and MEMS using flip chip.

Both flip-chip and wire bonding suffers from the large parasitic capacitance; the main source of the capacitance is the pad capacitance, which depends on the size of the pad area. Pad size of the bond wire can be as large as 100 μm × 100 μm, and the resulting capacitance ranges from 300 to 500 fF (Krishnamoorthy and Goossen, 1998; Kisiel and Szczepanski, 2005). For a more advanced assembly ­process, 35 μm × 35 μm pitch pads are possible and result in 200–300 fF in pad capacitance (Agarwal and Karim, n.d.). Also, these parasitics are in addition to the on-chip wire parasitics that may be used in redistributing signals to the edge of the chip or even to the pads slightly away from the devices.

Due to the limited wire pitch possible on the package substrate and also the limited bond wire density, this method of integration makes it difficult to integrate a large array of MEMS/sensors. Also, hybrid integration cannot be done in batch, as it is possible with monolithic integration; each chip must be assembled individually to the package substrate, and if the wire bonding technology is used, individual bond wire must be interconnected one at a time using a serial process. This serial nature of the process increases the unit cost significantly.

3.3.3  Emerging Method of Integration and 3D Integration of CMOS and MEMS

Despite the availability of monolithic and hybrid integration methods in the industry however, there exists a huge segment of market that is yet to be exploited. This stems from the fact that the two integration methods force drastic compromise between performance and cost. Monolithic provides high-performance integration at the cost of material and process flexibility and integration complexity, while hybrid integration provides relatively simple integration with a significant reduction in performance.

Recently, a new method of integrating MEMS has been proposed (Yang et al., 2010; Lee et al., 2011); by leveraging the 3D integration technologies, it may be possible to provide the performance matching the monolithic integration, and at the same time allow separate fabrication of CMOS IC and MEMS, lifting the severe material and process limitations. By fabricating CMOS IC and MEMS chip independently, assembling them on top of each other and making vertical interconnections, MEMS designers are no longer restricted to a narrow process window available with monolithic integration nor the low-performance routing and redistribution wires used in a package-based integration (Figure 3.4).

However, 3D integration of CMOS and MEMS has potential to do more than just address the problems of conventional integration methods – it can provide new features. For example, as discussed in Yang and Bakir (2010) and Yang et al. (2010), separating the MEMS and CMOS IC into physically different chips makes it possible for one to discard and replace one of the chips during both the assembly process and during the lifetime of the system. For biosensor systems, where sensors may be contaminated often, this means that only sensor chip can be replaced while the CMOS IC is reused.

3D integration of CMOS and MEMS require advanced I/O and 3D bonding technologies.

Figure 3.4   3D integration of CMOS and MEMS require advanced I/O and 3D bonding technologies.

The 3D integration of MEMS also provides a good opportunity to address common issues in MEMS integration – stress. By interconnecting the MEMS die with CMOS IC using an advanced interconnect technology that allows isolation of stress, it may be possible to reduce the thermo-mechanical stress experienced by the MEMS devices significantly. For example, flexible interconnects have a potential to provide such capability (Figures 3.5 and 3.6).

However, before one can leverage 3D integration for MEMS integration, many interconnect challenges must be resolved. The first is the problem of making sure that the MEMS and sensors are facing away from the package. This is important as some sensors require exposure to the environment or the sealing techniques for MEMS require that the chips face outwards. If the chip faces towards the package, the presence of underfill or die-attach adhesive may have an unwanted effect on the MEMS device. This is a challenge, because stacking two chips require that signals from one side of the chip be routed to the other side the chip – a TSV technology is needed.

3D integration of CMOS and MEMS using solder ball array.

Figure 3.5   3D integration of CMOS and MEMS using solder ball array.

3D integration of CMOS and MEMS using MFI technology.

Figure 3.6   3D integration of CMOS and MEMS using MFI technology.

3.4  Flexible I/Os and MFIS

The concept of flexible structures as interconnects has been around for a while. The motivation for such technology is due to the presence of the package substrate that plays a vital role in protecting MEMS chips from various contaminants and provides mechanical support; unfortunately, one side effect of having a composite structure with various materials, fabricated, assembled and operating at various temperatures, is stress.

Beginning with multiple generations of works called sea of leads (SoL) (Bakir et al., 2002; Dang et al., 2006), SoL aimed to mitigate thermo-mechanical stress issues mainly by providing lateral compliance and lateral range of motion, and later work also included ways to provide few micrometres of stand-off height and therefore some vertical compliance, by using a sacrificial layer process. G-helix (Lo and Sitaraman, 2004), FlexConnect (Kacker and Sitaraman, 2008, 2009) and β-helix (Zhu et al., 2003) are other examples of continued works in this area. Other examples of compliant interconnects are discussed in Fjelstad (1998), Novitsky and Pedersen (1999), Fjelstad et al. (2000), Kim et al. (2001) and Bakir and Meindl (2008).

However, these flexible interconnects have been designed to address a very specific problem present in the CMOS IC packaging; many focus on the reliability issues due to thermo-mechanical stress. However, unlike stress in MEMS where even a small amount of stress can drastically change the device characteristics, for CMOS, one was more worried about physical destruction of the IC. The mechanical characteristics of the flexible I/O for MEMS integration required were very different, and a new flexible I/O technology was needed.

Exactly how significant does the stress affect MEMS? Package-induced stress actually may have a devastating effect on the performance of MEMS device, and various methods have been proposed and are being used to reduce the effect of stress on the MEMS device. For example, in Lishchynska et al. (2007), as much as 37% change in the performance was reported as a result of packaging stress.

One proposed solution for addressing the stress issue is by taking into account the effect of the package-induced stress during the design stage of MEMS devices. By utilizing finite element models (FEM), it has been shown to be able to predict the chip warpage caused by both die-attach adhesive and ball grid array flip-chip processes and take into account the change in the geometry of the MEMS devices after the packaging. For example, the effects of package-induced stress were determined using simulations as shown in studies by Walwadkar et al. (2003) where 3.5 mm by 3.5 mm silicon dies were attached to ceramic package substrates using silver glass and polymide adhesives.

Once the simulation shows how and to what degree the package-induced warpage of the chip affects the MEMS devices, one can either modify the device design to reduce the impact of the warpage to the performance of the MEMS chip or sometimes even incorporate the warpage in determining the MEMS geometries.

However, these simulations do not take into account the dynamic nature of the stress; the degree of chip warpage caused by the stress changes not just during the manufacturing process but also throughout the life cycle of the chip due to the viscoelastic nature of the adhesive material used, as well as varying conditions in which the system operates.

For example, in Joo and Choa (2007), the coefficient of thermal expansion (CTE) mismatch between Si chip and package substrate caused, on average, 80 Hz resonance frequency shift in MEMS gyroscopes, where a frequency shift of 30 Hz was considered to substantially degrade the sensor performance such as sensitivity and phase change resulting in yield loss or failure. It was only after several changes in the design and the material used for the device that the authors were able to achieve a frequency shift of 20.7 Hz.

In MEMS integration, flexible interconnects can provide benefits in multiple fronts other than relieving stress.

First, flexible interconnects can be used to compensate for nonplanar surfaces that may exist, and source of nonplanarity could be on the substrate as well as from the inherent limitation of solder deposition method (Basavanhally et al., 2007) or other bonding mechanisms.

Second, flexible interconnects can be used to make temporary interconnections enabling the idea of reusable electronics where the CMOS IC can be reused while the sensor chip is disposed. For areas where sensors are often irreversibly contaminated, or if the cleaning of the sensors does not make an economic sense, this ability to replace the sensor chip only can potentially bring down the cost of operation. An example of such area is the biosensor application, where sensors can be contaminated by blood or other biohazardous materials (Ravindran et al., 2010; Yang et al., 2010). It can also be used for interconnecting a macro-chip with nano-photonics and proximity I/Os (Shubin et al., 2009).

In both instances, one requires flexible interconnect structures to have a higher stand-off height and also a vertical range of motion that utilizes all of the available stand-off height.

 

Case Study: MFIS

Mechanically flexible interconnect (MFI) is a flexible I/O technology developed at Georgia Tech that aims to provide MFI as much vertical range of motion as possible (50 μm) and also to provide benefits discussed in the previous section. In order to do this, the latest generation of MFIs has incorporated several design features.

  • Tapered Interconnect Structure In order to minimize the plastic deformation of the flexible interconnect structure during vertical deformation, a tapered interconnect design was used instead of a more common constant width design; by linearly varying the width of the beam, it is possible to distribute the stress more uniformly. This lowers the maximum stress experienced by the beam as shown in the ANSYS simulation. Figure 3.7 shows the reduction in the peak stress experienced by the structure due to the tapering shape.
  • Curved Beam Design In order to allow the 100% of the stand-off height to be utilized, it was also necessary to diverge from the conventional cantilever design as shown in Figures 3.8 through 3.10. With such design, the range of motion would be restricted to the height of material deposited on the tip of the beam, which in this case was the height of the solder ball. By having a curved beam design, this problem can be avoided and it is the design used for the MFIs.
  • Use of High-Yield Point Material and Oxidation Prevention Copper is a good material for interconnects as it has a very low resistivity. However, there are two main challenges for using copper for the flexible interconnects. The first is the low-yield point of copper, which can cause reliability issues at large deformation, and the second is the issue of oxidation, as copper readily oxidizes at room temperature. For the new generation of MFIs, an alternative material (nickel/tungsten alloy) was used to improve the yield characteristic, and surfaces of the structures were passivated by electroless gold plating to minimize oxidation (Zhang et al., 2012).

Solder Confinement

Though MFIs can be used to provide temporary interconnects as discussed previously, if it is to be used for permanent interconnection, the ability to fabricate solder ball on it becomes critical. However, due to the entire structure being metal, solder must be properly confined so that it does wet the entire structure during the bonding process; wetting the entire interconnect structure would cause unexpected mechanical behaviour and therefore inconsistent assembly results. A polymer ring was formed on the pad area as shown in Figure 3.11, and the solder was deposited in the middle. Figure 3.12 shows that the solder is confined to the pad area only after reflowing. The polymer rings also allow electroplating of various UBM metals underneath the solder; in this work, nickel is used as a UBM.

 ANSYS FEM simulation comparing the tapered design (a) with the constant width design (b) of the interconnect structures. The tapered design results in more uniform distribution of stress. (© 2012 IEEE.)

Figure 3.7   (See colour insert.) ANSYS FEM simulation comparing the tapered design (a) with the constant width design (b) of the interconnect structures. The tapered design results in more uniform distribution of stress. (© 2012 IEEE.)

Comparing curved beam design and conventional cantilever design for use in flexible interconnects. (© 2012 IEEE.)

Figure 3.8   Comparing curved beam design and conventional cantilever design for use in flexible interconnects. (© 2012 IEEE.)

Scanning electron microscope (SEM) image showing the curved profile of a MFIs. (© 2012 IEEE.)

Figure 3.9   Scanning electron microscope (SEM) image showing the curved profile of a MFIs. (© 2012 IEEE.)

Microscope and SEM images showing various versions of MFIs. (© 2012 IEEE.)

Figure 3.10   Microscope and SEM images showing various versions of MFIs. (© 2012 IEEE.)

 Confining of a solder ball at the tip of MFIs using polymer rings. (© 2012 IEEE.)

Figure 3.11   (See colour insert.) Confining of a solder ball at the tip of MFIs using polymer rings. (© 2012 IEEE.)

SEM showing the confined solder ball after the reflow process. (© 2012 IEEE.)

Figure 3.12   SEM showing the confined solder ball after the reflow process. (© 2012 IEEE.)

3.4.1  Fabrication of MFI

The process can be performed at the wafer level and are processes that can be implemented following the end of the semiconductor BEOL processes. This allows MFIs to be fabricated on CMOS chips. Figure 3.13 shows an overview of the MFI fabrication process.

The first part of the process is the fabrication of the curved polymer surface. This is done by spin coating a photo-definable sacrificial polymer and then reflowing it. Though the shape of the curved polymer surface is created almost instantly, the reflowed polymer then needs to be cured at 150°C in order to increase the glass transition temperature (Tg) and to remove excess solvent.

Increasing the glass transition temperature of the polymer is critical, as initial glass transition temperature is below many of the baking temperatures of the photoresists used in the following processes. The optimal curing time and temperature were experimentally determined. Details of the experiment as well as the fabrication process can be found in Yang and Bakir (2012). The second part of the process is to deposit an electroplating seed layer on top of the reflowed polymer. The third part of the process is to spin coat and pattern an electroplating mould for the electroplating of the interconnect beam structure. Nickel/tungsten alloy (or copper) is then electroplated. After the electroplating process, the electroplating mould is removed. SU-8 polymer ring is then formed and another electroplating mould with an opening inside the polymer ring is formed. Nickel and solder are then electroplated, respectively. Finally, the seed layer is removed followed by the removal of the sacrificial polymer (using acetone), which releases the MFIs. MFIs are then coated with gold using electroless gold plating process.

Process flow for the fabrication of MFIs. (© 2012 IEEE.)

Figure 3.13   Process flow for the fabrication of MFIs. (© 2012 IEEE.)

3.4.2  Mechanical Testing of MFI

Mechanical testing of the MFIs was done with an indenter setup (Figure 3.14) that can measure the vertical displacement as a function of the force applied. The results are shown in the Figure 3.15. Two important results can be seen from the aforementioned results. The first is that the compliance of the MFIs is predictable using simulations (ANSYS FEM) and can be engineered easily by changing the thickness, which can be done quite easily by adjusting the electroplating time required. The second is that the range of the compliance that can be achieved with MFIs is quiet wide.

MFI compliance requirements are not the same for all applications. Variables such as the size of the chip and number of I/Os determine the mechanical requirements of individual MFI properties, and the ability to predict the properties allows MFI to be used for wide range of applications.

In order to verify that the MFIs are not yielding during the operation, one of the MFIs was indented multiple times. The graph in Figure 3.16 shows that the mechanical characteristics of the MFI remain unchanged.

Test setup for measuring the compliance of a single MFI. (© 2012 IEEE.)

Figure 3.14   Test setup for measuring the compliance of a single MFI. (© 2012 IEEE.)

Graph showing the simulated and measured compliance of MFIs. (© 2012 IEEE.)

Figure 3.15   Graph showing the simulated and measured compliance of MFIs. (© 2012 IEEE.)

Graph showing the change in the mechanical compliance of MFIs after 2 months with and without gold coating. (© 2012 IEEE.)

Figure 3.16   Graph showing the change in the mechanical compliance of MFIs after 2 months with and without gold coating. (© 2012 IEEE.)

3.5  TSV for MEMS

As discussed in the previous section, TSV is a vital technology if MEMS is to be integrated vertically (3D). This is because, there exists many cases where the MEMS devices must be placed on the top chip facing outwards; for example, the MEMS sensor may require an interaction with the material it is trying to sense.

Though many TSV technologies have been explored by many for fabrication in CMOS ICs, TSV in MEMS chip presents vastly different challenges. First, TSV technology for MEMS must be compatible with thicker chips (typically thicker than 300 μm), as MEMS chips are rarely thinned down like a CMOS IC. Second, in order to not restrict the MEMS fabrication in terms of processes and materials, TSV must be able to be fabricated after the MEMS device.

3.5.1  Challenges of Fabricating TSVs in Thick Chip

3.5.1.1  Stress

A TSV generally consists of a metal conductor in vertical direction through silicon and thin dielectric liner between the metal and the silicon. Various materials like copper, tungsten, nickel and aluminium can be used as metal in TSVs. Copper is mostly used for the TSV metal part because of the ease of fabricating high-aspect-ratio TSVs in chips as well as in silicon interposer packages using electroplating, better electro-migration resistance and comparatively lower resistivity. But CTE of copper is almost seven times higher than that of silicon. This induces higher stress in silicon surrounding the copper as well as causes reliability issues for the TSV structure when thermal load is exerted on TSVs. Moreover, the previous section discusses the significant effect stress has on the performance of MEMS devices.

TSV stresses increase as TSV diameter increases and the nature of these stresses is dependent on the relative arrangement of TSVs (Lu et al., 2009; Jung et al., 2011), and because the processes in TSVs are aspect ratio limited, a TSV in thick MEMS chips requires that the diameter be very large compared to TSVs in thin CMOS ICs.

Increased TSV stress can affect five regions in and around TSVs: silicon, copper, silicon dioxide, copper–silicon dioxide interface and BEOL layers near TSVs. Firstly, due to increased stress in silicon, mobility of carriers in silicon changes that can affect the operation of MOSFETS in the regions near TSVs. This creates requirement of keep-out zones around TSVs to ensure the desirable operation of MOSFETS as well as MEMS devices. The keep-out zone increases as TSV stresses increase (Lu et al., 2009; Athikulwongse et al., 2010). Moreover, higher stress in silicon may also lead to crack formation and propagation in silicon (Lu et al., 2009). Secondly, due to increased TSV stresses, cohesive cracks can form and propagate in silicon dioxide as well as in copper. Thirdly, increased stresses at copper–silicon dioxide interface can lead to interfacial crack propagation and interfacial delamination of the copper in TSVs (Andry et al., 2008; Liu et al., 2009).

To reduce the effect of TSV stresses, there are several ways including effective stress-aware placement of TSVs (Liu et al., 2009; Jung et al., 2011), using TSV conducting material (e.g. tungsten) with CTE comparable to that of silicon (Andry et al., 2008; Bauer et al., 2009), introducing and optimizing pre-chemical mechanical polishing (CMP) anneal to reduce copper pumping (Malta et al., 2011; Wolf et al., 2011) or using a thick stress buffer polymer cladding between copper and silicon in TSVs instead of thin silicon dioxide liner to form polymer-clad TSVs (Parekh et al., 2011). In polymer-clad TSVs, when a thick polymer material is selected with lower Young’s modulus compared to silicon and copper, the polymer can absorb stress caused by the CTE mismatch between the silicon and the copper. Various modelling results have been shown for polymer-clad TSVs to show reduction in TSV stresses (Chen et al., 2009; Jung et al., 2011; Ryu et al., 2011). In addition to reduction in TSV stresses, a significant reduction in TSV dielectric capacitance can be obtained using polymer material with lower dielectric constant and with appropriate cladding thickness (Civale et al., 2011).

For cladding purpose, various materials have been investigated in literature including SU-8, parylene, BCB, epoxy and polymide. The cladding fabrication process can be by vapour deposition of polymer (e.g. parylene coating) (Majeed et al., 2008), filling of etched areas in silicon followed by selective silicon etching to form vias with cladding (Civale et al., 2011) or photodefinition of polymer filled in etched vias in silicon (Thadesar et al., 2012). In case of parylene deposition, limited thickness may be obtained. In case of filling etched trenches, the filling process would be dependent on aspect ratio of trenches (the higher the aspect ratio, the difficult is the filling) as well as on viscosity of polymer to be filled (difficult to fill polymers with higher viscosity). However, the process of filling via openings with polymer and later photo-defining the polymer can be used to fabricate high-aspect-ratio polymer-clad TSVs for chips as well as silicon interposer packages, using polymers with various range of viscosities (e.g. SU-8).

Thadesar et al., (2012) fabricated SU-8-clad TSVs with 120 μm outer diameter, 80 μm inner diameter (20 μm thick annulus-shaped SU-8 cladding) and 390 μm tall for silicon interposer application (Figures 3.17 and 3.18). The 80 μm inner diameter of TSVs meets ITRS 2010 projection of 80 μm diameter vias for silicon interposers for high-performance computing systems for the year 2017. SU-8 is a widely used photoresist for fabrication of high-aspect-ratio structures (Campo and Greiner, 2007). Young’s modulus of SU-8 is very low (4 GPa) as compared to that of silicon (185 GPa) and copper (117 GPa). Consequently, SU-8 can act as a stress buffer layer between silicon and copper relieving TSV stresses. Along with stress reduction, due to 20 μm thick cladding of SU-8 with relative dielectric constant ∼3 (silicon dioxide relative dielectric constant is 3.9), considerable reduction in TSV capacitance can be obtained compared to TSVs with same copper diameter, same length and with thin silicon dioxide liner.

Microscope image showing the SU-8-clad TSVs (top view). (From Thadesar, P.A. and Bakir, M.S., Silicon interposer featuring novel electrical and optical TSVs, in

Figure 3.17   Microscope image showing the SU-8-clad TSVs (top view). (From Thadesar, P.A. and Bakir, M.S., Silicon interposer featuring novel electrical and optical TSVs, in ASME International Mechanical Engineering Congress and Exposition (IMECE), 2012, Houston, TX.)

Microscope image showing the SU-8-clad TSVs (cross-sectional view). (From Thadesar, P.A. and Bakir, M.S., Silicon interposer featuring novel electrical and optical TSVs, in

Figure 3.18   Microscope image showing the SU-8-clad TSVs (cross-sectional view). (From Thadesar, P.A. and Bakir, M.S., Silicon interposer featuring novel electrical and optical TSVs, in ASME International Mechanical Engineering Congress and Exposition (IMECE), 2012, Houston, TX.)

3.6  Seed-Layer Fabrication

Large-diameter TSVs that result due to the thick chips create a fabrication challenge. Typically a TSV is filled using an electroplating process and requires a seed layer to be fabricated. Many conventional TSV processes have fabricated this seed layer as shown in the Figure 3.19 as follows.

After the via hole etch using a DRIE, the seed layer is formed by first depositing a metal layer around the via area and electroplating until the via holes are closed. The thick bulk metal formed is then polished before via is filled. Both the ‘pinch off’ time and the polishing time is a very time-consuming process.

Lai et al. (2010) introduced an alternative method called mesh process that eliminates this process. This process starts with the deposition of SiO2 layer where the TSVs will be formed. SiO2 is used as the stop layer for the DRIE via hole etch. In the suspended SiO2 layer, a mesh is patterned and etched as shown in the Figure 3.19. A metal layer is evaporated on top and then electroplated. A short electroplating session is enough to close up the mesh holes, creating a seed layer through the mesh layer in which the TSVs can be electroplated from. The fabrication results show that the presence of mesh does not create voids during the electroplating process.

Conventional process flow for fabricating seed layer for electroplating up TSV in thick wafers. (From Lai, J.-H., Yang, H.S., Chen, H. et al., 2010, A “mesh” seed layer for improved through-silicon-via fabrication,

Figure 3.19   Conventional process flow for fabricating seed layer for electroplating up TSV in thick wafers. (From Lai, J.-H., Yang, H.S., Chen, H. et al., 2010, A “mesh” seed layer for improved through-silicon-via fabrication, J. Micromech. Microeng., 20, 025016, 2012. Copyright 2012, Institute of Physics.)

3.7  Elimination of CMP for Post-Mems TSV Fabrication

As discussed previously, fabricating TSV must be done post-MEMS in order to not restrict MEMS devices in terms of processes and materials that can be utilized. However, most TSV processes require chemical and mechanical planarization (CMP) to be performed on the side where sensitive MEMS device may be present. Conventional TSV process flow requiring CMP process is shown in Figure 3.20. For a post-MEMS fabrication of TSVs, a new planarization method is needed.

In Lai et al. (2010), a chemical planarization method is introduced that can be used safely with a wide range of MEMS devices already present on the substrate. The process involves the use of second type of metal, different from the via material, and exploits the mesh process introduced in the previous section. The process begins after the fabrication of seed layer. Instead of using the seed layer to fill up the via completely with copper, a thin layer of nickel is electroplated first. After the nickel electroplating, the copper is electroplated. Then, the side without SiO2 is covered and the sample is placed in a chemical copper etchant bath, and because nickel does not etch in the copper etchant, the etch stops when the copper seed layer is removed and nickel layer is exposed in the via. The process flow is shown in the Figure 3.21.

Without the mesh process, there exist two mechanical polish steps on one side (the side with the seed layer) and another one on the opposite side. By using mesh to pinch off, the need for thinning down the bulk metal seed layer is eliminated, and by using two-metal chemical planarization technique, the need for the mechanical planarization is also eliminated. Therefore, if one fabricates MEMS devices on the side where the mesh is present, this process allows TSVs to be fabricated post-MEMS.

Conventional process flow for filling via holes for TSV requires CMP that can damage sensitive devices. (From Lai, J.-H., Yang, H.S., Chen, H. et al., 2010, A “mesh” seed layer for improved through-silicon-via fabrication,

Figure 3.20   Conventional process flow for filling via holes for TSV requires CMP that can damage sensitive devices. (From Lai, J.-H., Yang, H.S., Chen, H. et al., 2010, A “mesh” seed layer for improved through-silicon-via fabrication, J. Micromech. Microeng., 20, 025016, 2012. Copyright 2012, Institute of Physics.)

TSV fabrication using the mesh seed-layer process eliminates the need for the CMP process. (From Lai, J.-H., Yang, H.S., Chen, H. et al., 2010, A “mesh” seed layer for improved through-silicon-via fabrication,

Figure 3.21   TSV fabrication using the mesh seed-layer process eliminates the need for the CMP process. (From Lai, J.-H., Yang, H.S., Chen, H. et al., 2010, A “mesh” seed layer for improved through-silicon-via fabrication, J. Micromech. Microeng., 20, 025016, 2012. Copyright 2012, Institute of Physics.)

3.8  Summary

The 3D integration of CMOS and MEMS provides the performance of monolithic integration and the process simplicity of hybrid integration. The key to exploiting all the benefits of 3D integration for CMOS and MEMS is in leveraging advanced interconnect technologies such as flexible interconnects and TSVs. In this chapter, the motivation and need for such interconnects are discussed as well as overview of challenges involved in design and fabrication of such interconnects.

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