# Variability in Scaled MOSFETs

Authored by: Toshiro Hiramoto

# Nanoscale Silicon Devices

Print publication date:  December  2015
Online publication date:  January  2016

Print ISBN: 9781482228670
eBook ISBN: 9781482228687

10.1201/b19251-4

#### 3.1  Introduction

For the past 40 years, the size of metal-oxide-semiconductor field-effect-transistors (MOSFETs) has been scaled down in order to attain higher performance, lower power dissipation, and higher integration in large-scale integrated circuits (VLSI). It is well known that the miniaturized size of MOSFETs has brought about various technical issues including short channel effects, degraded reliability due to a high electric field, and performance degradation due to parasitic resistance and capacitance. Among them, one of the most significant technical problems is the variability of transistor characteristics [14]. Owing to the transistor variability, the circuits do not function correctly even though each individual transistor behaves correctly, or the margin in the circuit operation is reduced causing manufacturing yield to drop precipitously. This problem of the variability in characteristics may impose a limit on the transistor scaling, performance improvement, and power dissipation reduction. Therefore, it is an urgent issue to understand the root causes and find solutions. However, the origins that lead to variability in characteristics cover a very wide range from atomic-level impurity distribution to ­manufacturing equipment. The understanding of the physics behind the variability problems and the development of effective measures to the problems are essential.

In this chapter, the present status of the transistor variability is reviewed. In particular, the random variability and its impact on static random access memory (SRAM) are described. As a solution to the variability issue, a fully-depleted (FD) silicon-on-insulator (SOI) transistor with intrinsic channel is described. A new concept for the suppression of random variability in SRAM is also introduced.

#### 3.2  Variability in 65 nm Transistors

In this section, the status and basic behaviors of transistor variability are illustrated by taking the 65 nm planar bulk technology as an example.

#### 3.2.1  Classification of Transistor Variability

There are so many types of transistor variability in VLSI. Figure 3.1 schematically shows the classification of transistor variability. The transistor characteristics differ from one lot to another. This is lot-to-lot variability (or interlot variability). Within the same lot, the transistor characteristics differ from one wafer to another (wafer-to-wafer variability or interwafer variability). Within the same wafer, transistor characteristics differ from one chip to another (chip-to-chip variability or interchip variability). Even in the same chip, the transistor characteristics differ from one transistor to another (intrachip variability).

Figure 3.2 shows an example of intrawafer variability and intrachip variability of transistors fabricated by the 65 nm bulk planar technology [5]. A large number of transistors were measured using a device-matrix-array (DMA) test-element group (TEG). Each chip has one million (1M) transistors with identical gate length (L) and gate width (W). In order to show the overall and systematic variability within the wafer and chip, each datum point in Figure 3.2 represents the average threshold voltage (Vth) of 1k transistors (each wafer has 1k data points). Apparently, some chips have higher Vth, and others have lower Vth. This is the chip-to-chip variability. There is also a Vth variation within a chip. It is found that the magnitude of the intrawafer variability is larger than that of the overall within-chip variability.

Figure 3.1   A schematic diagram of interlot, interwafer, interchip, and intrachip variabilities.

Figure 3.2   Measured Vth variability of nFETs in a wafer and in a chip. Each chip has 1M nFETs. Average Vth’s of 1k transistors are shown (each wafer has 1k data points). (From Tsunomura, T. et al., Jpn. J. Appl. Phys., 48, 124505, Copyright 2009 The Japan Society of Applied Physics.)

Figure 3.3a shows detailed intrachip variability of the 65 nm transistors, where each datum point corresponds to Vth of each transistor [5]. Surprisingly, Vth differs largely from one transistor to another. The measured Vth values are mathematically separated into a random component and systematic component in Figure 3.3b and c [5]. It is found that the random component is much larger than the systematic component. These results indicate that as long as the transistor layout patterns are regular and identical, the random component is dominant and the systematic component is negligible in the planar bulk transistors.

Figure 3.3   (a) Measured Vth variability of 1M nFETs within a chip. (b) Separated systematic component. (c) Separated random component. (From Tsunomura, T. et al., Jpn. J. Appl. Phys., 48, 124505, Copyright 2009, The Japan Society of Applied Physics.)

#### 3.2.2  Dependence on the Number of Transistors

The range of the random variability depends on the number of transistors. Figure 3.4a shows I–V characteristics of 100 n-type transistors (nFETs) within a chip. Gate length L is 60 nm and gate width W is 120 nm. Clear Vth variability is found, but the range of Vth is not so wide. The cumulative plot of Vth is also shown. The Vth data lie on an almost straight line and Vth ranges within ±2.6σ, where σ is the standard deviation and approximately 43 mV in this wafer. When the number of transistors increases by 100 times (10,000 transistors), I–V characteristics are varied as shown in Figure 3.4b. The Vth range increases to ±3.8σ.

When the number of transistors increases further by 100 times (1M transistors), I–V characteristics are shown in Figure 3.4c [5], where the Vth range further increases to ±5σ. It is also clearly shown that since Vth data lie on a straight line in the cumulative plot, Vth follows the normal distribution up to ±5σ, and therefore, the variability is random. Vth ranges over a wide range from −0.28 to 0.73 V, which may cause severe yield loss and margin degradation in circuit operation.

1M nFETs in other chips in the same wafers and other wafers were also measured. Although the average Vth’s are slightly different from one chip to another, Vth also follows the normal distribution up to ±5σ in all chips and σ is almost the same (not shown). From these results, the transistor variability in lots, wafers, and chips is schematically shown in Figure 3.5. The intrawafer variability is smaller than the interlot variability. Each wafer has different average Vth and each chip also has different average Vth. The within-chip variability is defined by the average Vth and σ. It is also found that Vth follows the normal distribution up to ±5σ in pFETs and the variability in nFETs is larger than that in pFETs [5,6] (not shown).

Figure 3.4   Measured I–V characteristics and cumulative Vth distribution of (a) 100 nFETs, (b) 10,000 nFETs, (c) 1M nFETs. L = 60 nm and W = 120 nm. (From Tsunomura, T. et al., Jpn. J. Appl. Phys., 48, 124505, Copyright 2009, The Japan Society of Applied Physics.)

Figure 3.5   A schematic distribution showing the relationship among interlot, interwafer, interchip, and within-chip variabilities.

#### 3.2.3  Origin of Random Variability

In order to examine the origins of the aforementioned huge random variability of measured Vth, the transistors that exhibit extreme Vth values are directly observed by the transmission electron microscope (TEM) [6]. Figure 3.6 shows a top view and the cross-sectional TEM images of −5σ, median, and +5σ nFETs. Observed gate oxide thickness (tox), measured strain, and images of gate polysilicon grains are also shown. It is surprising to find that transistor sizes (L, W, and tox) of −5σ FET and +5σ FET are almost identical even though Vth’s are so different. This result clearly suggests that the large random variability is not caused by the variation of transistor dimensions.

It is now well recognized that the origin of the random variability of transistor characteristics is the random dopant fluctuation (RDF). Vth of a transistor is primarily determined by dopant concentration in the depletion layer in the transistor channel. However, the number of dopants in the depletion layer varies from one transistor to another, causing the Vth variability. It is well known that when the dopants are randomly distributed, the number of dopants follows the Poisson distribution. When the number of dopants increases, the Poisson distribution is well approximated by the normal distribution. This is why the measured Vth follows the normal distribution.

Figure 3.6   Observations of nFETs that have extremely low Vth (−5σ), median Vth, and extremely high Vth (+5σ). Top view and cross-sectional TEM images, measured tox, measured strain, and observed poly-Si grains are shown. (Modified from Tsunomura, T. et al., Analyses of 5σ Vth fluctuation in 65 nm-MOSFETs using Takeuchi plot, Symposium on VLSI Technology, Honolulu, HI, 2008, pp. 156–157.)

#### 3.2.4  Size Dependence of Variability

When the random variability is dominant in the transistor variability, the standard deviation σ of transistor parameters has transistor size dependence. This phenomenon can be understood by the nature of the Poisson distribution. In a Poisson distribution, σ is given by $μ$

, where μ is the average number, and the normalized variability (σ/μ) is given by $1 / μ$ . In a smaller transistor, the number of average dopant atoms included in the depletion region is smaller, and hence, the normalized variability (σ/μ) of the dopant number is larger. When the transistor size increases, the variability of dopant number is averaged out and becomes smaller. Therefore, the variability of a transistor parameter increases as the transistor size is scaled down.

The average number μ of dopant atoms is proportional to LW, where L is the gate length and W is the gate width. Then, the variability is given by a simple function of $1 / LW$

[3]. Figure 3.7a shows σVth as a function of $1 / LW$ [7]. When tox is fixed and only transistor size is varied, measured data lie on the same straight line. The slope of this line is often called Pelgrom coefficient (Avt) and this figure is called Pelgrom plot [3]. Then, σVth is given by $σ V th = A vt / LW$ . This is a very useful equation. When Avt of a semiconductor process is known and the transistor size is fixed, σVth is easily derived.

Figure 3.7   (a) Pelgrom plot of measured σVth of nFETs with various sizes and tox. The slope is defined as Avt. (b) Takeuchi plot of measured σVth of nFETs with various sizes and tox. The slope is defined as Bvt. (Tsunomura, T. et al., Process condition dependence of random Vth variability in NFETs and PFETs, International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan, pp. 1010–1011, Copyright 2009 The Japan Society of Applied Physics.)

It is known that Avt depends on gate oxide thickness tox and NA. In order to develop a more universal relationship between σVth and transistor parameters, it is proposed to use the Takeuchi plot [8]. Figure 3.7b shows a Takeuchi plot, where the data in Figure 3.7a is replotted [7]. The horizontal axis is $T inv ( V th + V 0 ) / LW$

, where Tinv is the electrical gate oxide thickness at inversion and V0 is given by −(VFB + 2φF), where VFB is the flat band voltage and φF is the Fermi energy. Even though tox and NA are different, all data lie on the same straight line. The slope of Takeuchi plot is defined as Bvt. This Takeuchi plot indicates that σVth increases as Vth becomes higher. The Takeuchi plot is useful when σVth should be obtained in different Vth.

#### 3.2.5  Drain Current Variability

Drain current variability, as well as Vth variability, is a major concern in VLSI, because it directly causes huge variations in memory and logic circuit performances. Figure 3.8a shows I–V characteristics of 1M nFETs fabricated by 65 nm bulk technology. Large drain current variability is observed [9]. Figure 3.8b shows the cumulative plot of the on-current (Ion), which shows that Ion also follows the normal distribution up to ±5σ. Obviously, the origins of drain current variability are Vth variability and Gm variability. However, it has been found that there is a third origin of drain current variability [9].

Generally, there are two definitions of threshold voltage. One is the threshold voltage defined by subthreshold constant current (I0 = 10−7 × W/L). This threshold voltage is called Vthc in this study. The other is the threshold voltage determined by extrapolating drain current (Vgs intercept of tangent line with largest slope in Ids–Vgs characteristics). This is called Vthex.

Figure 3.9 shows I–V characteristics of two nFETs, which have identical Vthc and Gm [9]. Ion differs significantly even though Vthc and Gm are the same. Please note that the onset point of drain current in the linear scale plot is different, and therefore, Vthex is quite different in these two nFETs. Here, we define “current onset voltage (COV)” as COV = Vthex − Vthc [9,10]. The drain current rises rapidly and Ion is high when COV is small, while the drain current rise is slower when COV is large. Therefore, the COV variability contributes to the Ion variability.

Figure 3.8   (a) Measured I–V characteristics of 1M nFETs. (b) Cumulative plot of the on-current (Ion) of 1M nFETs. (Modified from Tsunomura, T. et al., Analysis and prospect of local variability of drain current in scaled MOSFETs by a new decomposition method, VLSI Symposium on Technology, Honolulu, HI, 2010, pp. 97–98.)

It has been found that Vthc, Gm, and COV are almost mutually independent [9]. Then, Ion variability can be separated into three components of Vthc, Gm, and COV. Figure 3.10 shows the decomposition of measured Ion variability [9]. Ion variability (σIon) is normalized to median Ion, and the decomposition of σIon/Ion is shown. It is found that Vthc is the major component of Ion variability, and COV is the second biggest component in the saturation region (Vds = 1.2 V) and is larger than the Gm component. To suppress the Ion variability, the understanding and suppression of COV variability is indispensable.

Figure 3.9   Measured I–V characteristics of two nFETs with identical Vthc and Gm, showing the difference of COV. (Modified from Tsunomura, T. et al., Analysis and prospect of local variability of drain current in scaled MOSFETs by a new decomposition method, VLSI Symposium on Technology, Honolulu, HI, 2010, pp. 97–98.)

Figure 3.10   Decomposition of measured Ion variability of nFETs into Vthc, Gm, and COV components. (a) Saturation region at Vds = 1.2 V. (b) Linear region at Vds = 0.05 V. (Modified from Tsunomura, T. et al., Analysis and prospect of local variability of drain current in scaled MOSFETs by a new decomposition method, VLSI Symposium on Technology, Honolulu, HI, 2010, pp. 97–98.)

#### 3.2.6  Origin of COV Variability

Why is COV not constant and fluctuates from one transistor to another? This is because the current path in the subthreshold region and strong inversion region is different. In a planar bulk MOS transistor, the channel potential fluctuates due to RDF. The subthreshold current flows in the potential valley, which is often called the percolation path. Therefore, Vthc, which reflects the subthreshold current, is determined by how deep the potential valley is. In the strong inversion region, on the other hand, the potential fluctuation by RDF is screened by inversion charges. Therefore, Vthex, which reflects the strong inversion current, is determined by the average potential of the channel.

Figure 3.11   (See color insert.) Simulated potential distribution in the transistor channel and the potential on the “dividing line” along the channel width direction. (a) The transistor with the smallest COV among 200 pFETs. (b) The transistor with the largest COV among 200 pFETs. (Modified from Kumar, A. et al., Origin of “current-onset voltage” variability in scaled MOSFETs, IEEE Silicon Nanoelectronics Workshop, Honolulu, HI, 2010, pp. 7–8.)

In order to examine the aforementioned model of COV, 3D device simulation is performed. Assuming RDF, I–V characteristics of 200 transistors are simulated. Among them, two transistors, which have the smallest COV and the largest COV, are selected. Figure 3.11 shows simulated potential of the “potential dividing line” along the channel width direction [10]. It is clearly shown that the transistor with the smallest COV has only shallow potential valleys, while the transistor with the largest COV has a very deep potential valley. The potential depth (the difference between average and minimum channel potential) is also simulated. It is found that while Vthc and Vthex have poor correlation with the potential depth, COV has a strong correlation with the potential depth [10] (not shown). These results confirm the model that the COV variability is caused by the potential fluctuation due to RDF.

#### 3.3  Variability of 11G Transistors

Generally, the ideal normal distribution of Vth is assumed to predict the yield of large-scale integrated circuits and memories in the circuit simulation. In the previous sections, it is shown that Vth follows the normal distribution up to ±5σ in both nFETs and pFETs [5,6]. However, the state-of-the-art VLSI chips contain more than 1G (one billion) transistors in a chip. To our best knowledge, Vth distributions of 1G-level transistors have not been reported, mainly because the measurement takes an overwhelmingly long time. Therefore, the 6σ distribution is still unknown. In this section, a special DMA-TEG for ultrafast Vth monitoring is designed and fabricated, and 10G-level transistor variability is measured and the distribution is analyzed [11,12].

Figure 3.12   A schematic diagram of fast Vth monitoring circuit for measuring 11G transistors. (Modified from Mizutani, T. et al., Measuring threshold voltage variability of 10G transistors, International Electron Devices Meeting (IEDM), Washington, DC, 2011, pp. 563–566.)

#### 3.3.1  Measurement of 11G Transistors

Figure 3.12 shows a schematic of the fast Vth monitoring circuit using the amp mode [11]. The device under test (DUT) is selected by a decoder and the current, IDUT, is compared with the constant current, IREF. The gate force voltage, VGF, is scanned at an interval of 25 mV, and VGF at which IDUT exceeds IREF is defined as measured Vth. Please note that the measured Vth is Vthc, instead of Vthex. The designed DMA TEG has 256M transistors in a chip, and the measurement time is approximately 3 h per chip.

DMA TEG chips were fabricated by the 65 nm technology. Gate length L is 60 nm and gate width W is 120 nm. IREF is set to 100 nA. Vth’s of 44 chips were measured, and therefore, the total number of transistors is 11G (11 billion), which corresponds to 6.5σ. After Vth’s of all transistors were measured and Vth distribution of 256M transistors was determined in each chip, I–V characteristics were also measured only for transistors with extremely high Vth or low Vth (beyond ±5.0σ) and median Vth in order to investigate the origin of nonnormal distribution of Vth.

#### 3.3.2  Vthc Variability of 11G Transistors

Figure 3.13 shows measured cumulative plots of Vth of 11G nFETs and pFETs at |Vds| = 50 mV [11]. It has been found that nFETs show good normality up to more than ±6.5σ, although slight deviation is observed in the low Vth region below −4σ. This is the first observation of Vth distribution of 10G-level transistors. On the other hand, pFETs also have an almost normal distribution in the high Vth region up to more than 6.5σ. However, apparent distribution “tail” is observed in the low Vth region below −4σ. This large “tail” may affect the yield of large-scale logic circuits and SRAM, and determining the cause is urgent.

Figure 3.13   Measured cumulative distributions of Vth of 11G transistors at |Vds| = 50 mV. (a) nFETs and (b) pFETs. (Modified from Mizutani, T. et al., Measuring threshold voltage variability of 10G transistors, International Electron Devices Meeting (IEDM), Washington, DC, 2011, pp. 563–566.)

Figure 3.14 shows measured I–V characteristics at |Vds| of 50 mV and 1.2 V of some of the transistors with extremely high Vth and low Vth (beyond ±5.0σ) [11]. For transistors with extremely low Vth, apparently larger drain-induced barrier lowering (DIBL) is observed in both nFETs and pFETs. In particular in pFETs, degraded subthreshold slope (SS) is observed. In order to examine the DIBL degradation in more detail, DIBL distribution of 1000 transistors in the extremely low Vth region (below −5.0σ), medium Vth, and extremely high Vth region (above 5.0σ) is measured [11] (not shown). Clearly, transistors in low Vth region have anomalously large DIBL in both nFETs and pFETs. However, a clear difference between nFET and pFET is not found in DIBL.

Figure 3.14   Examples of measured I–V characteristics at |Vds| of 50 mV and 1.2 V with extremely high Vth and low Vth (beyond ±5.0σ). (a) nFETs and (b) pFETs. (Modified from Mizutani, T. et al., Measuring threshold voltage variability of 10G transistors, International Electron Devices Meeting (IEDM), Washington, DC, 2011, pp. 563–566.)

Figure 3.15   Distributions of measured COV in extremely low Vth region (below −5.0σ), medium Vth, and extremely high Vth region (above 5.0σ). (a) nFETs and (b) pFETs. (Modified from Mizutani, T. et al., Measuring threshold voltage variability of 10G transistors, International Electron Devices Meeting (IEDM), Washington, DC, 2011, pp. 563–566.)

We found pronounced differences of characteristics in COV between nFET and pFET. Figure 3.15 shows distributions of measured COV in extremely low Vth region (below −5.0σ), medium Vth, and extremely high Vth region (above 5.0σ) [11]. Again, transistors in low Vth region have anomalously large COV in both nFET and pFET. Especially in pFETs, COV of low Vth transistors is abnormally large. This result indicates that the distribution tail observed in pFET is closely related with degraded COV and may be caused by local percolation paths that are formed in the regions with extremely small number of dopants due to RDF, which will be discussed again later.

#### 3.3.3  Vthex and Ion Variability of 11G Transistors

It is impossible to measure Vthex of all 11G transistors, because I–V curve measurements are necessary to derive Vthex, which takes an extremely long time. By measuring I–V characteristics of low Vthc region and high Vthc region with additional measurements of I–V characteristics of another 4k transistor TEG (which corresponds to the distribution center), the distribution of Vthex is derived [12]. Figure 3.16 shows cumulative plots of measured Vthex of 11G nFETs and pFETs at |Vds| = 50 mV [12]. It is newly found that Vthex does not have a long distribution tail, contrary to Vthc, even in pFETs. Although Vthc has an impact on the standby power, circuit operations and performance are mainly affected by Vthex rather than Vthc. Therefore, one expects that the impact of the long Vthc distribution tail on circuit design is minimal.

Figure 3.16   Cumulative distributions of measured Vthex of 11G transistors at |Vds| = 50 mV. (a) nFETs and (b) pFETs. (Modified from Mizutani, T. et al., Analysis of transistor characteristics in distribution tails beyond ±5.4σ of 11 billion transistors, International Electron Devices Meeting (IEDM), Washington, DC, 2013, pp. 826–829.)

Using a similar method, the Vthc and Ion distributions at Vds = 1.2 V are determined [12]. As expected, Vthc has a long tail in low Vthc region at |Vds| = 1.2 V even in nFETs (not shown), because DIBL is very large in low Vthc region. Figure 3.17 shows cumulative plots of measured Ion of 11G nFETs and pFETs at |Vds| = 1.2 V [12]. nFETs have much larger Ion variability than pFETs, because Vth variability in nFETs is larger than that in pFETs. Moreover, Ion deviates from the normal distribution in the low Ion region in both nFETs and pFETs. Some transistors have abnormally low Ion, which may have a greater impact on circuit performance and yield. It is found that |Vthc| of the FETs with lowest Ion is not necessarily the highest in both nFET and pFET [12] (not shown), indicating that the origin of abnormally low Ion is not high Vthc but some other mechanisms such as extraordinarily high contact resistance.

Figure 3.17   Cumulative distributions of measured Ion of 11G transistors at |Vds| = 1.2 V. (a) nFETs and (b) pFETs. (Modified from Mizutani, T. et al., Analysis of transistor characteristics in distribution tails beyond ±5.4σ of 11 billion transistors, International Electron Devices Meeting (IEDM), Washington, DC, 2013, pp. 826–829.)

#### 3.3.4  SS Variability of 11G Transistors

Subthreshold swing (SS) is one of the most important parameters, which determine the off-current of transistors. In spite of the importance, few experimental data [13] have been reported on the variability of SS. Looking at I–V curve in Figure 3.14 carefully, SS in high subthreshold current (SS7′, at 3 × 10−7 × (W/L)A) is apparently degraded and fluctuates significantly in low Vthc region in pFET, although SS in deep subthreshold region (SS8, at 1 × 10−8 × (W/L)A) is not degraded. It is also found that SS7′ has very poor correlation with DIBL [12] (not shown), indicating that the degradation of SS7′ is not caused by the short channel effect. Moreover, degraded SS7′ has very good correlation with degraded COV [12] (not shown).

In order to examine the reason that SS7′ is degraded but SS8 is not degraded in low Vthc region, 3D device simulation was performed assuming two types of deep potential valleys in the transistor channel as shown in Figure 3.18a [12]. It is found that when the valley is narrow enough, punch-through is prevented. Although SS in high subthreshold current region is degraded, better SS in deep subthreshold region is obtained, as shown in Figure 3.18b [12]. These results indicate that the narrow potential valleys caused by RDF are responsible for degraded SS and degraded COV in high subthreshold current region.

Figure 3.18   (a) Potential distribution of the three transistor channels assumed in the sim­ulation. (b) Simulated I–V characteristics of the three transistors. (Modified from Mizutani, T. et al., Analysis of transistor characteristics in distribution tails beyond ±5.4σ of 11 billion transistors, International Electron Devices Meeting (IEDM), Washington, DC, 2013, pp. 826–829.)

#### 3.4  Stability of Sram Cells

The instability in SRAM cells due to the variability of individual transistors in the cells is known as a crucial problem that will prevent further device integration and Vdd lowering [14]. The yield and the minimum operating voltage (Vmin) are mainly determined by SRAM cells in recent VLSI. Therefore, the analysis of cell imbalances at the transistor level is essential for better understanding of SRAM stability at low Vdd. In this section, static noise margin (SNM) of SRAM cells and Vth of six individual transistors in the cells are directly measured and their variability is intensively analyzed using a DMA TEG of 16 kbit SRAM cells.

#### 3.4.1  Variability of Static Noise Margin

Figure 3.19 shows a schematic of the 16 kbit SRAM DMA-TEG [15]. The TEG is based on the transistor DMA TEG that we have developed [5,6]. DUT is connected to six switch transistors, so that DUT is electrically isolated from other devices. DUTs are arrayed in a matrix manner and each DUT can be accessed by using decoder circuits. In the present SRAM DMA TEG, DUT is replaced by an SRAM mini array of 6 × 8 cells. Terminals of Vdd, word line (WL), left bit line (BLL), right bit line (BLR) as well as two internal storage nodes (VL, VR) at the center cell of the SRAM miniarray are connected to the six switched transistors and can be accessed, and the rest of SRAM cells are dummy cells. Since the internal storage nodes are accessible, noise margins as well as characteristics of the 6 individual transistors can be directly measured. The 16 kbit SRAM DMA TEG was fabricated with 65 nm technology.

Figure 3.19   A schematic diagram of SRAM DMA-TEG and the circuit of six-transistor SRAM. (Modified from Hiramoto, T. et al., IEEE Trans. Electr. Dev., 58, 2249, 2011.)

I–V characteristics of 1k access NMOS transistors (Ta), drive NMOS transistors (Tn), and PMOS transistors (Tp) were measured [15] (not shown). The transistor characteristics vary significantly. The normal distributions of Vth’s of Ta, Tn, and Tp are confirmed. It is also confirmed that Tp has a smaller Vth variability than Ta and Tn.

Figure 3.20a shows measured butterfly curves of 1 kbit SRAM cells at Vdd of 1.2 V [15]. The WL is set to Vdd. There are huge variations of the butterfly curves. Here, one-side SNM is defined: SNM(L) is the square of the left eye of the butterfly curve, and SNM(R) is the square of the right eye. Please note that the SNM is defined as the smaller square of two eyes of the butterfly curve. Figure 3.20b shows cumulative distribution of measured 16 kbit SNM at several values of Vdd [15]. It is found that, while the one-sided SNM follows the normal distribution up to ±4σ even when Vdd is lowered from 1.2 to 0.4 V [15] (not shown), SNM does not follow the normal distribution. It is also shown that SNM is degraded when Vdd decreases and some cells fail at Vdd of 0.4 V.

#### 3.4.2  Vdd Dependence of SNM

Figure 3.21 shows measured SNM as a function of Vdd [15]. Among 16 kbit SRAM cells, cells that have SNM values between 0.20 and 0.21 V at Vdd of 1.2 V are selected, and their Vdd dependences are shown. It is very interesting to note that, even though SNM at 1.2 V is very similar, the Vdd dependence is very different depending on the cell: some cells show improvement of SNM when Vdd is lowered down to 0.8 V, and some cells show very severe degradation of SNM when Vdd decreases. At Vdd of 0.4 V, SNM of some cells remains at a high value above 0.1 V, but some cells fail (SNM is 0 V).

Figure 3.20   (a) Measured butterfly curves of 1 kbit SRAM cells at Vdd = 1.2 V. (b) Cumulative distributions of measured 16 kbit SNM at several values of Vdd. (Modified from Hiramoto, T. et al., IEEE Trans. Electr. Dev., 58, 2249, 2011.)

Figure 3.21   Measured SNM as a function of Vdd in SRAM cells whose SNM values are between 0.20 and 0.21 V at Vdd = 1.2 V. (Modified from Hiramoto, T. et al., IEEE Trans. Electr. Dev., 58, 2249, 2011.)

However, it has been found that this peculiar Vdd dependence is not simply explained by Vth variability alone [15]. Actually, when taking the variability of cell transistors into account in the circuit simulation, only Vth variability is generally considered. The circuit simulation results of SNM or Vmin are not necessarily consistent with the measured data [15]. Therefore, the effects of transistor parameters other than Vth should be examined.

#### 3.4.3  DIBL Dependence of SNM

In order to investigate the impact of device parameters on SNM, a unique method using a half-cell is employed [16]. The 16 kbit SRAM has 32 kbit half-cells. Among 32 kbit half-cells, half-cells in which Vth’s of three transistors (Tn, Tp, and Ta) are within the median value ±10 mV are selected. As a result, 183 half-cells are selected. Then, the selected 183 half-cells have almost identical Vth’s for the three transistors and the effects of Vth variability are eliminated. It is found that there is no clear correlation between measured SNM of the selected half-cells and measured Gm [16] (not shown), indicating that Gm variability has no clear effect on SNM. It is also found that the body factor has no clear effect on SNM.

Figure 3.22 shows measured SNM of the selected half-cells as a function of measured DIBL of Tn and Tp [16]. Here, DIBL is defined by Vth(Vds = 50 mV) − Vth(Vds = 0.6 V). Apparently, SNM has a negative correlation with DIBL of Tn and Tp, and SNM is more degraded when DIBLs of Tn and Tp are larger. There is clear experimental evidence that DIBL variability degrades SRAM stability. This negative correlation was not found in Ta [16] (not shown). These results show that the DIBL variability should be taken into account to explain SNM variability and its Vdd dependence.

Figure 3.22   Measured SNM of the selected half-cells as a function of measured DIBL of Tn and Tp. (Modified from Song, X. et al., Impact of DIBL variability on SRAM static noise margin analyzed by DMA SRAM TEG, International Electron Devices Meeting (IEDM), 2010, San Francisco, CA, pp. 62–65.)

#### 3.5  Intrinsic Channel Fd Soi Transistors

The major origin of random Vth variability is RDF. It is reported that DIBL and COV variabilities are also caused by channel potential fluctuations due to RDF [9,10]. These results suggest that, if the dopant atoms are removed from the channel, not only Vth variability but DIBL variability and COV variability will be suppressed. In this section, intrinsic channel FD SOI MOSFETs were fabricated and their variability was compared with that of conventional bulk MOSFETs using DMA TEG.

#### 3.5.1  Vth And Drain Current Variability

Figure 3.23 shows a schematic of intrinsic channel FD SOI nFET and pFET [17,18]. The channels are not intentionally doped. The SOI is very thin (tSOI = 12 nm in this study) to suppress the short channel effect. The buried oxide (BOX) is also very thin (tBOX = 10 nm in this study), which enables us to control Vth by back bias. This device is also called a silicon-on-thin-BOX (SOTB) transistor [1719]. FD SOTB transistors were fabricated with 65 nm technology. For comparison, conventional bulk transistors, where the channels are doped (2 × 1018 cm−3), were also fabricated for reference. A poly-Si gate was used in both FD SOTB and bulk MOSFETs, while high-k/SiON gate dielectric was used to adjust Vth of FD SOTB transistors. Tinv is almost the same (approximately 2.6 nm). The gate length is 60 nm and gate width is 120 nm. The characteristics of both bulk and intrinsic channel FD SOTB transistors were measured using DMA TEG.

Figure 3.24 compares Id–Vgs characteristics of 1k transistors of bulk nFETs and intrinsic channel FD SOTB nFETs [20]. Apparently, FD SOTB transistors have a smaller variability. Figure 3.25 shows cumulative plots of Vthc in bulk and SOTB nFETs [20]. Vthc shows a normal distribution in both bulk and SOTB, and Vthc variability is suppressed in SOTB nFETs (σ = 17.8 mV in linear region) compared with bulk (σ = 37.5 mV). This is because the intrinsic channel FD SOTB transistors have a very small number of dopants in the channel.

Figure 3.23   A schematic diagram of an intrinsic channel FD SOI FET. The device is also called an STOB transistor. A bulk FET cointegrated with an SOTB FET is also shown in this figure. (From Sugii, N. et al., Ultralow-voltage operation SOTB technology toward energy efficient electronics, International Conference on Solid State Devices and Materials (SSDM), Fukuoka, Japan, pp. 736–737, Copyright 2013 The Japan Society of Applied Physics.)

Figure 3.24   Measured Id–Vgs characteristics of 1k transistors of (a) bulk nFETs and (b) intrinsic channel FD SOTB nFETs. (Modified from Mizutani, T. et al., Reduced drain current variability in fully depleted silicon-on-thin-BOX (SOTB) MOSFETs, IEEE Silicon Nanoelectronics Workshop, Honolulu, HI, 2012, pp. 71–72.)

Figure 3.25   Cumulative distributions of measured Vthc at Vds = 1.2 V in (a) bulk nFETs and (b) SOTB nFETs. (Modified from Mizutani, T. et al., Reduced drain current variability in fully depleted silicon-on-thin-BOX (SOTB) MOSFETs, IEEE Silicon Nanoelectronics Workshop, Honolulu, HI, 2012, pp. 71–72.)

Figure 3.26 shows cumulative plots of on-current (Ion) in bulk and SOTB nFETs [20]. The Ion current is normalized to median Ion and σIon/Ion is shown in the figure. Ion variability is also reduced in the FD SOTB transistors. It is found that not only Vthc variability suppression but also COV variability suppression contributes to the Ion variability reduction in FD SOTB transistors (not shown). Figure 3.27 compares simulated potential fluctuations of transistor channels in bulk and FD SOTB MOSFETs [21]. Thanks to the intrinsic channel, the potential of an FD SOTB transistor channel is very smooth, leading to the reduction of Vth and Ion variabilities as well as DIBL and COV variabilities.

Figure 3.26   Cumulative distributions of measured σIon/Ion at Vds = 0.05 V and Vds = 1.2 V in (a) bulk nFETs and (b) SOTB nFETs. (Modified from Mizutani, T. et al., Reduced drain current variability in fully depleted silicon-on-thin-BOX (SOTB) MOSFETs, IEEE Silicon Nanoelectronics Workshop, Honolulu, HI, 2012, pp. 71–72.)

Figure 3.27   (See color insert.) Simulated potential distributions of transistor channels in (a) bulk nFETs and (b) SOTB nFETs. (Modified from Hiramoto, T. et al., Suppression of DIBL and current-onset voltage variability in intrinsic channel fully depleted SOI MOSFETs, IEEE International SOI Conference, San Diego, CA, 2010, pp. 170–171.)

#### 3.5.2  Stability in Fd Sotb Sram

Small variability in FD SOTB transistors allows a drastically reduction in the operating voltage of FD SOTB SRAMs. Figure 3.28 compares the measured butterfly curves of 1 kbit bulk and FD SOTB SRAMs at Vdd of 0.4 V [22]. Some cells fail at 0.4 V in bulk SRAM, while all 1 kbit cells operate even at 0.4 V in FD SOTB SRAM. The minimum operation voltage (Vmin) of 48 kbit SRAM is reduced from 0.542 V in bulk to 0.290 V in FD SOTB (not shown) [22]. The intrinsic channel is essential to achieve ultralow voltage operation below 0.4 V in large-scale SRAM cell array.

Figure 3.28   Measured butterfly curves of 1 kbit cells at Vdd = 0.4 V: (a) bulk SRAM and (b) FD SOTB SRAM. (From Mizutani, T. et al., Jpn. J. Appl. Phys., 53, 04EC18, Copyright 2014 The Japan Society of Applied Physics.)

#### 3.6  SElf-Suppression of Variability

Even in the intrinsic channel FD SOI MOSFETs, variability remains, and the variability seems to be enhanced in the next generations as the transistor size shrinks. Therefore, a new concept to cope with the variability problem is strongly required. In this section, a postfabrication scheme for self-suppression of SRAM variability (or self-improvement of SRAM stability) is proposed [23] and experimentally demonstrated [24]. This concept requires techniques of nonvolatile Vth shift of transistors and Vth shifts with high voltage stress were utilized in the experiments.

#### 3.6.1  Mechanism of Self-Improvement

Figure 3.29 shows a schematic of a six-transistor SRAM cell [25]. The two storage nodes in the cell are named as VL and VR. In the self-improvement technique, the stress voltage is applied to the Vdd terminal of SRAM cell array. Vdd is raised from 0 V to the stress voltage (3.2 V in this study), keeping the word line (WL) at 0 V. The scan time (stress time) is only several seconds. Since the Vth shift of nFETs was small enough while the |Vth| shift of pFETs is much larger at a stress voltage of 3.2 V, the self-improvement technique in the retention operation is explained based on the pFET |Vth| shift in the following.

The SRAM cell is bistable in the retention condition when Vdd is high enough and can store one bit per cell. The storage node VR can be either “high” or “low” in the bistable operation. However, when Vdd is very low (e.g., 0.1 V), each SRAM cell is not bistable because of the unbalance of the four transistors that compose two inverters. This is caused by the Vth variability. Then, VR is fixed to only “high” in almost half of the cells at very low Vdd and VR is fixed to only “low” in the other cells. In this technique, Vdd is just scanned from 0 to 3.2 V.

Figure 3.29   A schematic diagram of a six-transistor SRAM cell. It is assumed that VR is fixed to “high” at very low Vdd. (From Hiramoto, T. et al., IEICE Trans. Electron., E96-C, 759, Copyright 2013 IEICE. With permission.)

At the beginning of Vdd scan (0 V), VR is fixed to “high” in almost half-cells. As an example, let us assume that a cell whose VR is fixed to “high” at the beginning of Vdd scan, as shown in Figure 3.29. This means that the strength to pull up VR is stronger than the strength to pull up VL in this cell. Therefore, TpR or TnL may be stronger (lower |Vth|) than TpL or TnR. Here, we call a pFET connected to the high node as “p-ON” and a pFET connected to the low node as “p-OFF”, because the former is at the on state and the latter is at the off state. Similarly, “n-ON” and “n-OFF” are defined. It should be noted that, if p-ON is weakened, the cell stability is certainly improved, because the strength to pull up VR is weakened. Therefore, it is shown in the following that p-ON is the stronger pFET (that should be weakened for cell stability improvement) and p-OFF is the weaker pFET (that should be strengthened).

Next, let us consider the situation where Vdd is raised to 3.2 V. The negative gate bias is automatically applied to only p-ON that is stronger, because this transistor is at the on state. This bias condition is just the same as that of negative bias temperature instability (NBTI) stress, as shown in Figure 3.30a. Positively charged interface traps are generated. Then, |Vth| of p-ON is selectively raised and this transistor is weakened. On the other hand, the bias condition of p-OFF, which is weaker, is shown in Figure 3.30b. It is known that |Vth| is raised by the off state due to negative charge generation in oxide near the drain, and this transistor is strengthened. As a result, the cell stability is improved [25].

Figure 3.30   Bias conditions of pFETs when high voltage is applied at the Vdd terminal: (a) p-ON at the ON-state and (b) p-OFF at the OFF-state. (From Hiramoto, T. et al., IEICE Trans. Electron., E96-C, 759, Copyright 2013 IEICE. With permission.)

#### 3.6.2  Measurements of |Vth| Shift by High Voltage Stress

SRAM DMA TEG was fabricated with 40 nm bulk technology and the self-­improvement technique was applied to 4 kbit SRAM cells. We pay attention to the |Vth| shift of p-ON and p-OFF. By checking “high” or “low” of VL and VR, it is easy to determine which pFET is p-ON or p-OFF. Figure 3.31a shows measured |Vth| shift of p-ON, which was originally stronger and should be weakened for the self-improvement [25]. It is found that a majority of p-ON transistors show positive |Vth| shift, indicating that p-ON is weakened. This positive |Vth| shift is caused by the NBTI stress.

Figure 3.31b shows measured |Vth| shift of p-OFF, which is weaker [25]. Almost all p-OFF transistors show negative |Vth| shift, indicating that p-OFF which was originally weak is strengthened by the high voltage stress. The shift is even larger than that of p-ON. The self-improvement mechanism works.

Figure 3.31   Measured |Vth| shifts of pFETs in 4 kbit SRAM cells. (From Hiramoto, T. et al., IEICE Trans. Electron., E96-C, 759, Copyright 2013 IEICE. With permission.)

Figure 3.31 shows that not all cells exhibit the favorable |Vth| shift, that is, some cells exhibit negative |Vth| shift of p-ON and positive |Vth| shift of p-OFF, which is the opposite direction to the self-improvement. It is found that cells that show the opposite |Vth| shift are originally stable cells [25] (not shown). It is thought that these cells are so stable that “high” or “low” of the storage nodes is not determined at the beginning of Vdd scan. As a result, p-ON and p-OFF are interchanged resulting in the opposite |Vth| shift. However, since these cells are still stable enough after the opposite |Vth| shift, this phenomenon does not result in yield loss of SRAM.

#### 3.6.3  Measurements of Self-Improvement of SRAM Stability

Figure 3.32 shows examples of measured butterfly curves in the retention condition (WL is 0 V) before and after applying high voltage stress [25]. Here, RetNM(L) is defined as the square of the left eye of the butterfly curve and RetNM(R) is the square of the right eye. RetNM is the smaller square of two eyes of the butterfly curve. The change of butterfly curves by the stress is explained in the following.

As mentioned in Section 3.6.1, VR is fixed to “low” or “high” at the beginning of the Vdd scan. In a cell in Figure 3.32a, “VR = low” is stable at low Vdd, and hence RetNM(R) is larger and RetNM(L) is smaller. The right pFET (TpR) is the p-OFF. When high voltage stress is applied, |Vth| of p-OFF is lowered, and the inverter curve by TpR and TnR moves in the right direction, as shown in Figure 3.32a. Similarly, raised |Vth| of p-ON moves the inverter curve by TpL and TnL down. In this way, both p-ON and p-OFF contribute to enlarge RetNM(L), resulting in the cell stability improvement.

Figure 3.32   Measured butterfly curves in the retention condition before and after applying high voltage: (a) a cell where “VR = low” is stable at low Vdd and (b) a cell where “VR = high” is stable at low Vdd. (From Hiramoto, T. et al., IEICE Trans. Electron., E96-C, 759, Copyright 2013 IEICE. With permission.)

In a cell in Figure 3.32b, on the other hand, “VR = high” is stable, and hence, RetNM(R) is smaller. In this specific cell, only negative Δ|Vth| of p-OFF contributes, but no Δ|Vth| of p-ON is observed. The cell stability of this cell is also improved, because RetNM(R) is enlarged.

Figure 3.33   Cumulative distributions of measured RetNM of 4 kbit SRAM cells before and after applying high voltage. (From Hiramoto, T. et al., IEICE Trans. Electron., E96-C, 759, Copyright 2013 IEICE. With permission.)

Figure 3.33 shows measured RetNM distributions before and after the high voltage stress to Vdd in 4k SRAM cells [25]. Clear improvement of RetNM is observed, particularly in the worst cell that have originally the smallest RetNM. Since Vmin is determined by the worst cell, this self-improvement technique largely contributes to the yield enhancement of SRAM cells.

#### 3.7  Conclusions

The present status of the variability in scaled transistors is reviewed. The variability of a large number of transistors is extensively measured, and it is shown that the main origin of random variability in bulk transistors is RDF. The relationship between cell transistor variability and cell stability in SRAM was analyzed. As an approach to variability suppression, two methods are described: (1) utilization of intrinsic channel FD MOSFET to avoid RDF and (2) novel self-improvement technique of SRAM stability. These results will largely contribute to further device scaling and further minimization of energy consumption in future VLSI.

#### Acknowledgments

A part of this work was performed under the MIRAI project, LEAP project, and ELP project supported by NEDO.

#### References

Hoeneisen B. and Mead C.A. . 1972. Fundamental limitations in microelectronics—I. MOS technology. Solid-State Electron. 15: 819–829.
Keyes R.W. . 1975. The effect of randomness in the distribution of impurity atoms on FET thresholds. Appl. Phys. 8: 251–259.
Pelgrom M.J.M. , Duinmaijer A.C.J. , and Welbers A.P.G. . 1989. Matching properties of MOS transistors. IEEE J. Solid-State Circuits 24: 1433–1440.
Kuhn K. , Giles M.D. , Becher D. 2011. Process technology variation. IEEE Trans. Electr. Dev. 58: 2197–2208.
Tsunomura T. , Nishida A. , and Hiramoto T. . 2009. Verification of threshold voltage variation properties in scaled transistors with ultra large-scale device matrix array test element group. Jpn. J. Appl. Phys. 48: 124–505.
Tsunomura T. , Nishida A. , Yano F. 2008. Analyses of 5σ Vth fluctuation in 65 nm-MOSFETs using Takeuchi plot. Symposium on VLSI Technology, Honolulu, HI, pp. 156–157.
Tsunomura T. , Nishida A. , Takeuchi K. 2009. Process condition dependence of random Vth variability in NFETs and PFETs. International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan, pp. 1010–1011.
Takeuchi K. , Fukai T. , Tsunomura T. 2007. Understanding random threshold voltage fluctuation by comparing multiple fabs and technologies. International Electron Devices Meeting (IEDM), Washington DC, pp. 467–470.
Tsunomura T. , Kumar A. , Mizutani T. 2010. Analysis and prospect of local variability of drain current in scaled MOSFETs by a new decomposition method. VLSI Symposium on Technology, Honolulu, HI, pp. 97–98.
Kumar A. , Mizutani T. , Shimizu K. 2010. Origin of “current-onset voltage” variability in scaled MOSFETs. IEEE Silicon Nanoelectronics Workshop, Honolulu, HI, pp. 7–8.
Mizutani T. , Kumar A. , and Hiramoto T. . 2011. Measuring threshold voltage variability of 10G transistors. International Electron Devices Meeting (IEDM), Washington DC, pp. 563–566.
Mizutani T. , Kumar A. , and Hiramoto T. . 2013. Analysis of transistor characteristics in distribution tails beyond ±5.4σ of 11 billion transistors. International Electron Devices Meeting (IEDM), Washington DC, pp. 826–829.
Mizutani T. , Yamamoto Y. , Makiyama H. 2013. Statistical analysis of subthreshold swing in fully depleted silicon-on-thin-buried-oxide and bulk metal-oxide-semiconductor field effect transistors. Jpn. J. Appl. Phys. 52: 04CC02.
Bhavnagarwala A.J. , Tang X. , and Meindl J.D. . 2001. The impact of intrinsic device fluctuations on CMOS SRAM cell stability. IEEE J. Solid-State Circuits 36: 658–665.
Hiramoto T. , Suzuki M. , Song X. 2011. Direct measurement of correlation between SRAM noise margin and individual cell transistor variability by using device matrix array. IEEE Trans. Electr. Dev. 58: 2249–2256.
Song X. , Suzuki M. , Saraya T. 2010. Impact of DIBL variability on SRAM static noise margin analyzed by DMA SRAM TEG. International Electron Devices Meeting (IEDM), San Francisco, CA, pp. 62–65.
Tsuchiya R. , Horiuchi M. , Kimura S. 2004. Silicon on tin BOX: A new paradigm of the CMOSFET for low-power and high-performance application featuring wide-range back-bias control. International Electron Devices Meeting (IEDM), San Francisco, CA, pp. 631–634.
Sugii N. , Iwamatsu T. , Yamamoto Y. 2013. Ultralow-voltage operation SOTB technology toward energy efficient electronics. International Conference on Solid State Devices and Materials (SSDM), Fukuoka, Japan, pp. 736–737.
Yamamoto Y. , Makiyama H. , Shinohara H. 2013. Ultralow-voltage operation of silicon-on-thin-BOX (SOTB) 2 Mbit SRAM down to 0.37 V utilizing adaptive back bias. VLSI Symposium on Technology, Kyoto, Japan, pp. T212–T213.
Mizutani T. , Yamamoto Y. , Makiyama H. 2012. Reduced drain current variability in fully depleted silicon-on-thin-BOX (SOTB) MOSFETs. IEEE Silicon Nanoelectronics Workshop, Honolulu, HI, pp. 71–72.
Hiramoto T. , Mizutani T. , Kumar A. 2010. Suppression of DIBL and current-onset voltage variability in intrinsic channel fully depleted SOI MOSFETs. IEEE International SOI Conference, San Diego, CA, pp. 170–171.
Mizutani T. , Yamamoto Y. , Makiyama H. 2014. Comparison and distribution of minimum operation voltage in fully depleted silicon-on-thin-buried-oxide and bulk static random access memory cells. Jpn. J. Appl. Phys. 53: 04EC18.
Suzuki M. , Saraya T. , Shimizu K. 2009. Post-fabrication self-convergence scheme for suppressing variability in SRAM cells and logic transistors. Symposium on VLSI Technology, Kyoto, Japan, pp. 148–149.
Suzuki M. , Saraya T. , Shimizu K. 2010. Direct measurements, analysis, and post-fabrication improvement of noise margins in SRAM cells utilizing DMA SRAM TEG. Symposium on VLSI Technology, Honolulu, HI, pp. 191–192.
Hiramoto T. , Kumar A. , Saraya T. 2013. Experimental demonstration of post-fabrication self-improvement of SRAM cell stability by high-voltage stress. IEICE Trans. Electron. E96-C: 759–765.

## Use of cookies on this website

We are using cookies to provide statistics that help us give you the best experience of our site. You can find out more in our Privacy Policy. By continuing to use the site you are agreeing to our use of cookies.