Yi Zhang and D. Brian Ma
Yi Zhang and D. Brian Ma
Driven by modern very large scale integration (VLSI) systems and their fast-emerging applications, the demands on multiple on-chip power supplies have been ever increasing due to two main reasons. First, as complexity of electronic devices such as cell phones and laptops increases, multiple power supplies are essential to power key functional blocks, such as processors, liquid crystal display, and radio transceivers. Second, as power consumption in semiconductor chips rises, efficient system power management techniques are in high demand. This leads to the high popularity of the so-called dynamic voltage/frequency scaling (DVFS) techniques (Burd et al. 2000, Chang and Pedram 1997, Cheng and Baas 2008, Ma and Bondade 2010, Usami et al., 1998), where multiple-supply-based power management schemes are crucial. By powering distinct functional modules and subsystems with different supply voltages and by adaptively switching their supplies according to instantaneous power needs, power and energy savings achieved through DVFS techniques are significant (Burd et al. 2000, Luo et al. 2007, Ma and Bondade 2010).
Historically, multiple DC power supplies are implemented by transformer-based isolated DC–DC converters or several nonisolated DC–DC converters. However, due to the use of bulky off-chip inductive components and many power switches, system volume, printed circuit board (PCB) footprint, and electromagnetic interference noise are all considerably large. In the meantime, regulation accuracy can be compromised by commonly used “master–slave” regulation approaches (Ma et al. 2001a).
To mitigate these issues, single-inductor multiple-output (SIMO) power converters were proposed (Ki and Ma 2001, Ma et al. 2001a, 2003a,b). By time-sharing a single inductor and some power switches, a SIMO power converter offers multiple power outputs, which can be regulated independently. This leads to a significant reduction in cost, volume, and PCB footprint. Because of their cost-effective features, the application of SIMO power converters has been proliferating in recent years, spanning from hybrid power source units (Huang et al. 2010), energy-harvesting systems (Kim and Rincon-Mora 2009, Sze et al. 2008) to light-emitting diode backlighting (Chen et al. 2012), active matrix OLED display panels (Chae et al. 2009), and electronic paper displays (Lee et al. 2010).
As more SIMO converter-based IC products are being commercialized in the market, cross-regulation effect, as one of the most critical design challenges, has drawn extensive attention. In a SIMO switching converter, because the inductor is time-shared by several subconverters, a duty ratio change in one subconverter may affect the amount of energy transferred to other subconverters even if the operating conditions (load currents, duty ratios, etc.) in other subconverters remain constant. As a result, this may cause voltage variations on the affected outputs. This effect was named as cross-regulation in Ma et al. (2003b) because a local operating condition change in one subconverter has impacted the regulation performances across the others. In worst-case scenarios, a SIMO converter fails to operate due to severe cross-regulation.
In order to avoid the cross-regulation effect, the regulation time slot designated to each subconverter should be completely isolated. For this reason, SIMO converters in the early stage usually operate in discontinuous conduction mode (DCM) (Ki and Ma 2001, Ma et al. 2001a, 2003b). However, in heavy-load scenarios, peak inductor current may rise very high in DCM, causing substantial voltage and current ripples and switching noise. Alternatively, if continuous conduction mode (CCM) is applied to alleviate large peak current, cross-regulation occurs immediately. In order to reduce the heavy current stress while retaining low cross-regulation, a pseudo-continuous conduction mode (PCCM) operation was first proposed in Ma et al. (2002). Instead of returning to zero as in DCM, the inductor current stays constant at a predefined current level through freewheel switching actions. With the same load condition, the peak inductor current in PCCM can be much lower than that in DCM, while still avoiding cross-regulation effect since the regulation actions on any two outputs are isolated by one freewheel switching period. Unfortunately, the PCCM operation also has its own drawbacks. Especially, in the unbalanced load conditions, large conduction power loss is observed in subconverters handling light loads. Moreover, since the freewheel switch turns on/off multiple times in one switching cycle, the overall switching power loss also increases. To overcome these drawbacks, a new control technique is required to reduce both conduction and switching power loss in the freewheel switch.
Figure 3.1 Power stage architecture and discontinuous conduction mode inductor currents of (a) two conventional switching power converters and (b) one single-inductor multiple-output converter. (From Zhang, Y., Single-inductor multiple-output power converters: Architectures, control techniques and applications, PhD dissertation, The University of Texas at Dallas, Richardson, TX, 2013.)
To better understand the PCCM operation for SIMO converters, we first examine the development of SIMO power converter, as illustrated in Figure 3.1 (Ma et al. 2001a, 2003b). Consider two conventional switching boost converters in DCM operating at the same switching frequency. One possible operation scheme is illustrated in Figure 3.1a. At the beginning of each switching cycle T, the inductor L1 is charged at a rate of VIN/L1 until D11T expires, where D11 is the duty ratio of the switching power converter 1. During D21T, the inductor L1 is discharged at a rate of −(VIN − VO1)/L1 and IL1 drops down until it returns to zero. The inductor current stays at zero during D31T. Similar operation scheme applies to the switching power converter 2.
If the two inductor currents can be alternately assigned to occupy different parts of the switching cycle without overlapping, only one single inductor will suffice for their operation, as shown in Figure 3.1b. During the first half switching cycle from 0 to T/2, the inductor current is diverted to VO1 by properly controlling the power switches SX and S1. Similarly, in the second half switching cycle, SX and S2 are turned on/off to deliver the inductor current to VO2. With this method, the inductor L is shared by the two subconverters in a time-multiplexing manner. Hence, a SIMO power converter with a time-multiplexing operation scheme is developed.
Obviously, this operation scheme can be readily extended for SIMO power converters with more than two outputs. For SIMO power converters with N subconverters, one switching cycle is divided into N phases, with the inductor current being multiplexed into each output during the corresponding phase. Furthermore, the topology is not only limited to boost converter. It can be easily extended to many existing switching power converter topologies (Ki and Ma 2001), such as buck and noninverting buck–boost.
It should be noted that the time-multiplexing operation is critical for a SIMO power converter. The inductor current is assigned to each subconverter alternately. Each output only occupies its own phase in one switching cycle. These phases are expected to be isolated in order to prevent cross-regulation. When the inductor current is being diverted into one subconverter, the other one is separated from the control loop. In other words, only one switching subconverter is being regulated at a time instant.
Similar to the conventional single-output switching power converters, the SIMO power converters can also be categorized into different types based on the topologies. In this section, the three primary topologies for SIMO power converters—boost, buck, and noninverting buck–boost topologies—are introduced.
The power stage architecture and timing diagram of a SIMO boost switching converter with two outputs are illustrated in Figure 3.2. The two subconverters are regulated by a pair of complementary clocks Φ1 and Φ2, with power delivered to each output from the supply VIN in a time-multiplexed manner. The working principle can be described with reference to the timing diagram illustrated in Figure 3.2b. When the first subconverter is operating, Φ1 = 1 and the switch S2 is off. No current flows into the output VO2. Meanwhile, SX is on. The voltage across the inductor is, thus, the supply voltage VIN. The inductor current IL increases during D11T:
Figure 3.2 (a) Power stage architecture and (b) timing diagram of single-inductor multiple-output boost converter.
During D21T, the switch SX is off and S1 is on, causing the inductor to discharge the current into the output VO1. The slope of the inductor current is given by
As the output voltage of a boost converter is greater than the supply voltage, the rate of the inductor current change is negative. As illustrated in Figure 3.2b, the inductor current decreases and delivers the required charge to the output. When it goes to zero, the converter enters D31T and the switch S1 is turned off. The inductor current stays at zero until the phase Φ2 begins. Hence, the duty ratios D11, D21, and D31 satisfy the requirements shown as follows:
During Φ2 = 1, the inductor current is multiplexed into the output VO2 and similar switching actions repeat for the subconverter 2. With this method, the two outputs are regulated in a time-multiplexing manner by sharing the inductor L and the power switch SX. Compared with two traditional switching boost converters, the number of off-chip magnetic component and power switches is both reduced. Obviously, with the increase of the number of subconverters, this cost reduction effect will become more significant.
Another primary type of SIMO power converters are constructed with buck topology. Figure 3.3a shows the power stage architecture of a SIMO buck power converter with two outputs. The power stage consists of one inductor L; four power switches SP, SN, S1, and S2; and two filtering capacitors CO1 and CO2. The two subconverters share the inductor L and power switches SP and SN. The timing diagram of DCM operation is illustrated in Figure 3.3b. Similar to the boost SIMO converter, the two subconverters are regulated alternately during Φ1 and Φ2. The two output voltages are stabilized at lower voltage levels than the input voltage, thereby achieving step-down DC–DC voltage conversions. The inductor current slope during charge and discharge periods is defined by
where i equals 1 or 2. Compared with two traditional buck converters, the number of inductors being used is halved. Although the number of power switches is not reduced, the cost effectiveness can still be observed when more subconverters are incorporated.
The third type of topology for SIMO power converters is noninverting buck–boost topology, which achieves both step-up and step-down voltage conversions. As shown in Figure 3.4a, the two subconverters share the inductor L and power switches SP, SN, and SX. The corresponding timing diagram is demonstrated in Figure 3.4b. In each phase, during the charge period, SP and SX are enabled, thereby charging up the inductor with a slope of VIN/L. Similarly, during the discharge phase, SN andSi are turned on. The inductor current ramps down with a slope of −VOi/L (i = 1 or 2). Compared with the boost and buck topologies, the noninverting buck–boost topology demonstrates higher flexibility regarding the voltage conversion ratios. The output voltage can be stabilized at higher, lower, or similar voltage levels compared with the input voltage. However, this flexibility is achieved at the cost of more power switches. The corresponding switching power loss and control complexity for noninverting buck–boost topology are, thus, increased compared with the other two topologies.
Figure 3.3 (a) Power stage architecture and (b) timing diagram of single-inductor multiple-output buck converter.
In addition to these three topologies, there are also other topologies that can be used in SIMO power converters. For example, inverting buck–boost topology allows the generation of negative output voltages. When combined with the aforementioned topologies, both positive and negative output voltages can be implemented. As a result, it leads to SIMO converters with bipolar power outputs (Ki and Ma 2001, Ma et al. 2001b).
Figure 3.4 (a) Power stage architecture and (b) timing diagram of single-inductor multiple-output noninverting buck–boost converter.
Historically, based on the inductor current, the operation mode for SIMO power converters can be categorized into two types: DCM (Ki and Ma 2001, Ma et al. 2001a, 2003b, Sze et al. 2008) and CCM (Belloni et al. 2008, Goder and Santo 1997, Li 2000, May et al. 2001). This section addresses both in due course, using a single-inductor dual-output (SIDO) boost topology as an example.
Figure 3.5 (a) Power stage architecture and (b) inductor current waveform of a single-inductor multiple-output boost converter operating in discontinuous conduction mode.
The typical inductor current waveform in DCM operation is shown in Figure 3.5. At the beginning of each phase, the inductor is charged. The charge process ends when D1iT expires, followed by a discharge period. Instead of occupying the rest of the phase, the discharge period, D2iT, ends once the inductor current drops to zero. After it, the inductor current stays at zero until the next phase is enabled. Since each subconverter only operates within its own phase, no two adjacent phases are overlapped, thereby eliminating the potential cross-regulation effect.
While the DCM operation can effectively suppress cross-regulation, it has certain drawbacks at heavy load conditions. With the same input/output voltages and load current, in order to deliver the same amount of charge with the same switching frequency, the peak inductor current value in DCM operation is usually much higher than in CCM. Hence, under heavy load conditions, DCM operation leads to large voltage/current ripples and switching noise.
Alternatively, another operation mode for SIMO power converters is CCM. As shown in Figure 3.6, the inductor is charged from the beginning of each phase. This charge process continues until the time period D1iT expires, where i equals 1 or 2. Then, the discharge period D2iT is enabled until the discharge phase ends. The inductor current charge and discharge actions are repeated in each phase, thereby delivering the desired power from input to the corresponding output. Since the next phase starts immediately after the current phase expires, the inductor current is kept continuous during the phase transition periods. Such type of operation scheme is thus called CCM.
Figure 3.6 Inductor current waveform of continuous conduction mode operation.
Due to the continuous conduction property, the inductor current is always maintained above zero. As a result, compared to the DCM operation, the CCM operation facilitates lower inductor current ripples, which in turn reduces output voltage ripples. Moreover, since the inductor current never goes to zero in CCM, the potential negative/reverse inductor current, which may occur in DCM operations, is avoided, thereby improving the power efficiency. From the circuit design perspective, the zero current detector and active diodes can be obviated. The circuit complexity and design challenge are both reduced.
However, CCM operation also incurs some drawbacks. Due to the continuous conduction property, the inductor current at the end of each phase is uncertain. As a result, the initial value of the inductor current to the second subconverter is dependent to the end value of the first one. If a sudden load change occurs in one phase, it will inevitably affect the subsequent phases, causing severe cross-regulation problems (Ma et al. 2003b).
In order to receive the benefits from both CCM and DCM operation schemes, the PCCM was proposed for SIMO power converters (Ma et al. 2002, 2003a). In the PCCM mode, as depicted in Figure 3.7 and similar to a CCM one, the inductor current of a SIMO converter always stays greater than a predetermined DC value Idc, thus reducing the inductor current ripples. This is achieved by shorting the inductor with the aid of a freewheel switch Sfw while keeping the other switches off. With reference to Figure 3.7, when Φ1 is enabled and during the period D21T, when the value of the inductor current reaches Idc, Sfw is turned on and all the other switches are turned off until Φ1 expires. This period is known as the freewheel switching period. A similar period occurs during Φ2. As the current continuously stays above Idc, it allows the converter to handle heavy current loads with low ripples. Moreover, since the two subconverters are isolated by the freewheel switching periods, cross-regulation is also avoided.
Figure 3.7 (a) Power stage architecture and (b) inductor current waveform of a single-inductor dual-output boost converter operating in pseudo-continuous conduction mode.
Despite the aforementioned advantages of PCCM operation, there remain some drawbacks. To avoid cross-regulation, the freewheel switching current level Idc has to be chosen to satisfy the largest load current among all the outputs. If the value of Idc is reduced, then a load change at either output could cause one of the subconverters to enter the CCM mode. For example, assume ILOAD1 suddenly increases. The inductor has to be energized to a larger current value in Φ1 to satisfy the higher power demand. IL, thus, may not be able to return to Idc before Φ1 expires. The converter then enters the CCM mode. Meanwhile, if the freewheel switching period DfwT is too long, the turn-on resistance of the freewheel switch and the direct current resistance (DCR) of the inductor can cause significant conduction loss. This is especially pronounced during unbalanced load conditions, as shown in Figure 3.8, in which a long DfwT can be observed in the light-load subconverter. Moreover, the switching power loss of Sfw also becomes significant when the number of subconverters is increased.
Figure 3.8 IL during pseudo-continuous conduction mode operation in unbalanced load condition.
To resolve the problems of traditional PCCM, adaptive PCCM operation schemes are developed (Zhang and Ma 2010, 2011, 2012b, Zheng et al. 2010). By adaptively adjusting the freewheel switching durations and the freewheel current level Idc, conduction power loss can be significantly reduced. Moreover, by switching Sfw only once per switching cycle, the switching power loss due to Sfw is also reduced. Since all the subconverters are still operating in PCCM, low cross-regulation can still be achieved.
Figure 3.9a models a freewheel switching loop. The resistance of the freewheel switch, RON, and the DCR of the inductor, RL, both contribute to conduction power loss. To simplify the analysis, the sum of RON and RL is named as REQ. Due to the voltage drop across REQ, IL during the freewheel switching period DfwiT (i = 1 or 2) decreases gradually as in Figure 3.9b. IL is, thus, given as
Consequently, the conduction power loss by Sfw is derived as
which reveals that the loss is highly related to Idc and the freewheel switching period.
Figure 3.9 (a) Circuit model and (b) the inductor current waveform of the freewheel switching. (From Zhang, Y. and Ma, D., J. Analog Integr. Circuits Signal Process., 72(2), 419, August 2012b.)
In addition to the conduction loss, a freewheel switch induces two types of switching losses: the V–I overlap power loss and the gate-drive power loss. The cause of V–I overlap power loss is illustrated in Figure 3.10b. Due to the parasitic capacitors (CGD and CGS in Figure 3.10a), the gate voltage Vgate of Sfw cannot step up/down abruptly, leading to the overlapping periods between nonzero voltage VSD and nonzero current ID. The converter loses power during such V–I overlapping transient periods. Meanwhile, as shown in Figure 3.10b, before/after the turn-on/turnoff events, a dead time is usually added to avoid shoot-through current. During such a dead time, all the power transistors are turned off and the inductor current flows through the body diode of Sfw. As a floating switch, Sfw is usually implemented with a PMOS power switch. The substrate of the PMOS switch Sfw is usually tied to the highest voltage in the system (Vmax), which is one of the output voltages in a SIMO boost converter (Ma 2007, Zhang and Ma 2012a, Zheng and Ma 2011). If the voltage drop across the body diode is neglected, VSD in Sfw swings between (Vmax −VIN) and ground. The turn-on process starts at t1 by discharging the gate capacitance. When the gate voltage drops to Vmax − VT at t2, Sfw starts to conduct current. When ID increases from zero to the full freewheel switching current Idc at t3, VSD starts to be pulled down. This continues until VSD drops to zero at t4.
Figure 3.10 (a) Circuit model and (b) key waveforms for switching power loss. (From Zhang, Y. and Ma, D., J. Analog Integr. Circuits Signal Process., 72(2), 419, August 2012b.)
The process ends when Vgate becomes zero at t5. The V–I overlap from t2 to t4 results in the corresponding energy loss Eon. This is calculated as
where tIR and tVF are the current rising time (t3 − t2) and voltage falling time (t4 − t3), respectively. Similarly, the turn-off transition reverses the sequence of the events and generates the turn-off V–I overlapping energy loss
where tVR and tIF are defined as the voltage rising time (t8 − t7) and current falling time (t9 − t8), respectively. For multiple-charge SIMO converters in PCCM, Sfw switches n times per switching cycle. The overall V–I overlap power loss is
where fsw is the switching frequency of the converter.
Another major switching power loss is the gate-drive power loss. This involves the charge/discharge processes on gate capacitors CGD and CGS. For CGD, the drain terminal is constantly connected to VIN and the gate voltage swings between Vmax and zero, leading to a traversed voltage of Vmax. But for CGS, the voltage of source terminal (VX) is tied to VIN during the conduction period and Vmax during the dead times. Meanwhile, the gate voltage is equal to zero and Vmax, respectively. The traversed voltage of CGS is then calculated as VIN. The gate-drive loss of freewheel switch can be derived as
The total switching power loss of Sfw, thus, can be denoted as
In conclusion, to achieve high efficiency in a SIMO converter operating in PCCM, the conduction and switching losses of the freewheel switch should be jointly minimized. These power losses are highly related to switching frequency of Sfw, freewheel switching current Idc and freewheel switching period.
To identify the optimal operation point, Figure 3.11 illustrates the inductor current IL in different operation conditions. The proposed adaptive PCCM operation scheme aims to provide a universal method to maintain this optimization in different load conditions. It should be noted that in any case each freewheel switching period should not be too short in order to prevent the converter from entering CCM. Neither should it be too long to cause large conduction loss. This is easy to achieve in balanced load conditions such as in Figure 3.11a. However, in unbalanced load conditions as in Figure 3.11b, due to the fixed phase durations, the freewheel switching period for the light-load output (Dfw2T) becomes much longer. The conduction loss of Sfw, thus, increases significantly. A straightforward way to reduce it is to lower the freewheel switching Idc level. However, since the phase durations are fixed, this may cause the other subconverter to enter CCM (Figure 3.11c), resulting in cross-regulation. Therefore, to maintain the optimal freewheel switching duration for each subconverter, both the phase durations and Idc level should be adaptively controlled (Figure 3.11d).
Figure 3.11 Inductor current waveform in pseudo-continuous conduction mode with (a) balanced loads, (b) unbalanced loads, (c) lowered Idc, and (d) adaptively controlled phase durations and Idc. (From Zhang, Y. and Ma, D., J. Analog Integr. Circuits Signal Process., 72(2), 419, August 2012b.)
The adaptive PCCM operation scheme with distributed freewheel switching is illustrated in Figure 3.12. Initially, the two phases of a SIDO converter are set equally as T/2, with a preset freewheel switching current at Idc. The duration of ΣDkiT is defined as
Figure 3.12 Adaptive pseudo-continuous conduction mode operation scheme with distributed freewheel switching. (From Zhang, Y. and Ma, D., J. Analog Integr. Circuits Signal Process., 72(2), 419, August 2012b.)
If the load current ILOAD1 of subconverter 1 suddenly increases (case (ii) in Figure 3.12), ΣDk1T is extended by ΔDT to accommodate this load power increase, resulting in a decreased freewheel switching duration in Φ1. The two freewheel switching periods are then equalized by adjusting the phase durations Φ1 and Φ2 in case (iii). Since this average freewheel switching duration is smaller than the optimal value, the Idc level is gradually increased to prolong the freewheel switching periods. Thus, the phase adjustment and Idc modulation take place iteratively to maintain the optimal freewheel switching durations. Similar actions apply when ILOAD1 suddenly decreases. To quantize the relation between phase duration, Idc, and the instant loads, the inductor current for a SIMO converter in PCCM with distributed freewheel switching is reexamined in Figure 3.13. Here, the ratio of D1i to D2i is defined by
where m1i and m2i are the slopes of IL and can be defined as
On the other hand, the total charge delivered to the ith output per switching cycle is calculated as
In steady state, it equals to the total charge demanded by the load ILOADi, which gives
Figure 3.13 IL with distributed freewheel switching. (From Zhang, Y. and Ma, D., J. Analog Integr. Circuits Signal Process., 72(2), 419, August 2012b.)
Alternatively, unified freewheel switching can be implemented, where the freewheel switching only occurs once per switching cycle. According to Equation 3.13, the switching power loss of Sfw can be reduced (Zhang and Ma 2011). This saving can be significant when the number of the subconverters in a SIMO converter is large.
Figure 3.14 Adaptive pseudo-continuous conduction mode operation scheme with unified freewheel switching. (From Zhang, Y. and Ma, D., J. Analog Integr. Circuits Signal Process., 72(2), 419, August 2012b.)
Here, a SIDO converter is employed as an example. If ILOAD1 suddenly increases from the steady state in case (i) in Figure 3.14, the corresponding phase duration of Φ1 is extended by ΔD1T to allow more inductor current to be delivered to VO1, thereby stabilizing VO1. Because of using the same start and end levels of the Idc, Φ2 is time-shifted until IL in Φ1 returns to Idc. The duration of Φ2 remains the same (as in case (ii)). Hence, the total current delivered to VO2 in each switching cycle remains unchanged through the adjustment on the duration of the freewheel switching. At the end, the variation ΔD1T is completely absorbed through the freewheel switching with a shorter freewheel switching duration (Dfw − ΔD1)T in case (ii). Similar adaptive operation process can be applied when ILOAD2 increases, as shown in case (iii). Conversely, if one load current is suddenly decreased, the corresponding phase duration will be reduced and the freewheel switching period will be prolonged (cases (v) and (vi) of Figure 3.14). It should be noted that, as the regulation period for each subconverter is not isolated from each other, risk of cross-regulation exists in this scheme.
In addition, the freewheel switching current level Idc also needs to be adjusted to maintain the optimal freewheel switching duration. In the proposed operation scheme, if the monitored freewheel switching duration is shorter than the desired value (cases (ii) and (iii) in Figure 3.14), the freewheel switching current will be gradually increased from Idc to a higher level, thereby recovering the optimal value of DfwT (case (iv) in Figure 3.14). This adjustment prevents the freewheel switching duration from disappearing (CCM) when a sudden load change occurs. Similarly, the freewheel switching current gradually decreases to a lower (case (vii) in Figure 3.14) when the freewheel switching duration is longer than the desired value (cases (v) and (vi) in Figure 3.14). It should be noted that the duration ratio between ) and ) in case (iv) (case (vii)) depends on the previous condition in case (ii) (case (v)) or case (iii) (case (vi)). Similarly, to quantize the relation between phase duration, Idc, and instant loads, the control equation can be obtained from Figure 3.15 such that
Figure 3.15 IL with unified freewheel switching. (From Zhang, Y. and Ma, D., J. Analog Integr. Circuits Signal Process., 72(2), 419, August 2012b.)
The proposed adaptive PCCM operations schemes are suitable for both digital and analog implementations. As digital design is usually portable to technology scaling and backed up by well-designed electronic design automation (EDA) tools, it always carries a great commercialization potential. Hence, a digital implementation is introduced first using the distributed freewheel switching scheme as major control algorithm. On the other hand, in many cases, analog approach can be very efficient in the aspects of silicon and power consumption. An analog implementation using unified freewheel switching scheme is, thus, discussed as well. In general, the proposed schemes are flexible to either digital or analog processing and can be virtually implemented in any fabrication processes.
Figure 3.16 shows the system block diagram of a SIDO boost converter, with the control scheme proposed in Section 220.127.116.11. The operation can be described with reference to Figure 3.17. Consider a SIMO converter has n subconverters. Initially, the phase period for each subconverter and freewheel switching Idc levels are set equal (Φ1 = Φ2 = … = Φn). As the load differs at each output, the freewheel switching duration in each phase differs accordingly.
Figure 3.16 Block diagram of an adaptive pseudo-continuous conduction mode single-inductor dual-output boost converter with digital distributed freewheel switching. (From Zhang, Y. and Ma, D., J. Analog Integr. Circuits Signal Process., 72(2), 419, August 2012b.)
Such a freewheel switching duration DfwiT (1 ≤ i ≤ n) is measured by a high-frequency digital counter, which also computes the average freewheel switching duration DavgT (=∑DfwiT/n). Each charge and discharge period (D1i + D2i)T is also measured. By adding DavgT to (D1i + D2i)T, the phase duration Φi for subconverter i in the next switching cycle is updated as
Figure 3.17 Implementation of the digital controller with timing diagram. (From Zhang, Y. and Ma, D., J. Analog Integr. Circuits Signal Process., 72(2), 419, August 2012b.)
In practice, the DavgT should not be too long in order to reduce conduction loss according to Equation 3.8. If it is longer than a predefined limit Dfw,maxT, the adjustment on freewheel switching Idc will be activated. Idc is then decreased by a step of (Idc,max − Idc,min)/2x for each cycle, where x represents the number of bits in the digital-to-analog converter (DAC) of Figure 3.17. As Idc decreases, (D1i + D2i)T extends to keep the delivered current to be the same as in the last switching cycle. As a result, the freewheel switching periods DfwiT in all subconverters decrease to reduce DavgT to be shorter than Dfw,maxT. Similarly, reverse adjustment steps will be taken if DavgT is smaller than Dfw,minT, which is at high risk of cross-regulation. Once the instant DavgT falls between Dfw,minT and Dfw,maxT, Idc adjustment is then completed. The iterative averaging on DfwiT leads the optimal operation eventually.
The adaptive PCCM operation scheme with unified freewheel switching is demonstrated through an analog implementation. In addition to the error amplifiers EAi to determine the peak inductor current for each subconverter, the analog controller includes an online analog charge meter to adaptively adjust Idc level, as shown in Figure 3.18. The inductor current is sensed by monitoring the currents flowing through MX, M1, and M2, which are then converted to voltage signals and compared with VEAOi and Vdc, thereby defining the duty ratios, phase durations, and freewheel switching durations. To explain the operating mechanism, a key voltage Vdc highlighted in Figure 3.18 is illustrated in Figure 3.19.
During the discharge period of D2iT in subconverter i (i = 1 or 2), Cdc in Figure 3.18 is charged by a constant current Ich. When a freewheel switching action occurs, a constant sink current Idch, which is equal to m × Ich, is activated to discharge Cdc. In steady state (solid line in Figure 3.19), it satisfies
Vdc keeps constant and an optimal freewheel switching duration can be achieved by setting an appropriate m value. If a load increase occurred in the last phase (Figure 3.19a), the corresponding charge and discharge periods of inductor current (and ) need to be extended in order to deliver more power. The freewheel switching duration ( ) is reduced accordingly, resulting in
Consequently, Vdc is increased toand a higher Idc level is thus achieved. Similarly, when a load decrease occurs, Vdc decreases due to
leading to a lower Idc level. On the other hand, when a load change occurs in the foregoing phase (Figure 3.19b), D11T and D21T show similar variations. Since the phase duration of subconverter 2 keeps constant (Φ2,, and are all equal), the variations are added to the freewheel switching period at the end of the switching cycle, thereby adjusting Vdc accordingly. With this method, Idc can be adaptively adjusted based on instantaneous load condition, thus improving the conduction loss. Moreover, the frequency of freewheel switching actions is significantly reduced, leading to the reduction of switching power loss.
Figure 3.18 Circuit detail of single-inductor dual-output converter with proposed analog controller. (From Zhang, Y. and Ma, D., J. Analog Integr. Circuits Signal Process., 72(2), 419, August 2012b.)
After the Vdc level is stabilized, the phase duration Φi of each subconverter is also automatically adjusted by the online charge meter. As shown in Figure 3.18, latch 1 is set by the clock signal CLK at the switching frequency of the SIMO converter. The discharge inductor current is sensed and converted to voltage signal Vs1. Once Vs1 becomes lower than Vdc, Φ1 expires and Φ2 is initiated by latch 2. Similarly, Φ2 expires when IL ramps down to Idc level.
Figure 3.19 Vdc adjustment with load variation occurring in (a) the last phase and (b) the foregoing phase. (From Zhang, Y. and Ma, D., J. Analog Integr. Circuits Signal Process., 72(2), 419, August 2012b.)
In this section, two adaptive PCCM operation schemes with the respective distributed and unified freewheel switching schemes were discussed. Compared with conventional PCCM operations, the phase durations and Idc level can be adaptively modulated, thereby maintaining optimal freewheel switching in various load conditions. As a result, power loss due to freewheel switching can be significantly reduced while retaining low cross-regulation effect. In addition, the two proposed operation schemes were implemented by both digital and analog methods. The advantages for each implementation method are also discussed respectively.
For the digital implementation, as most of the control circuits consist of the robust digital circuits, the system robustness across the process, voltage, and temperature (PVT) variations can be significantly improved. Moreover, with the development of modern VLSI techniques, digital circuits usually consume less silicon area compared with analog circuit counterparts.
On the other hand, by using the analog implementation method, the Idc level and phase durations for adaptive PCCM operation can be accurately fine-tuned. The adjustment resolution is thus well improved, resulting in more accurate control scheme. Based on the specific application background, the digital and analog circuit implementation, as well as the distributed/unified freewheel switching, can also be combined in different ways to define the most appropriate adaptive PCCM operation scheme for SIMO converters.